Internal Bus Interface Signals - Hitachi HD64465 User Manual

5.2.2

Internal Bus Interface Signals

Signal Name I/O Type
O
*RESET#
*STBY O
*WAIT# I
*MS# O
IMADDR[20:1] O
IMADDR24 O
IMADDR25 O
MIDATA[31:0] O
MODATA[31:0] I
IMRDWR# O
IMRD# O
IMWE0# O
IMWE1# O
IMWE2# O
IMWE3# O
Notes: 1. * stands for peripheral module name.
2. # means that a signal is active low.
Description
Internal Module Reset: This signal is module reset of *module. (For example,
LCDC reset signal is LCDC_RESET#)
Module Standby: This signal is used to control the standby mode for each
peripheral module. (For LCDC as an example, when LCDC_STBY is asserted,
LCDC module will go into the standby mode)
Module Wait: This signal is controlled by a peripheral module to insert a wait
state in CPU command cycle. (For LCDC as an example, when LCDC_WAIT#
is active low, the CPU Interface will insert a wait signal to the CPU cycle until
the LCDC_WAIT# is high)
Module Select: This module select signal is decoded based on the IPC
module address map. (For LCDC as an example, the LCDC control register
address and LCDC Frame buffer address will activate LCDC_MS# )
Internal Module Address Bus [20:1]: These are the address input signals to
all the peripheral modules. The peripheral module address decoder can use
these signals to decode the internal registers.
Internal Module Address bus 24: This signal is address bus number 24
driven by CPU Interface. This signal is connected to all peripheral modules.
Internal Module Address bus 25: This signal is address bus number 25
driven by CPU Interface. This signal is connected to all peripheral modules.
Module Input Data Bus [31:0]: These are the bit[31:0] of data bus to be
driven to all the peripheral modules. (Write data from the CPU)
Module Output Data Bus [31:0]: These are the bit[31:0] of data bus to be
read by the CPU. (Read data from the peripheral module)
Internal Module Read/Write Command: Internal Module read/write indicator
driven by CPU Interface.
Internal Module Read Command: When active along with *MS#, a valid data
MODATA[31:0] will be mapped onto the ODATA[31:0] for the Host CPU to
read. This signal is driven by CPU Interface.
Internal Module Write byte 0 Command: When active along with *MS#, a
valid data IDATA[7:0] will be passed from the Host CPU to MIDATA[7:0]. This
signal is driven by CPU Interface.
Internal Module Write byte 1 Command: When active along with *MS#, a
valid data IDATA[15:8] will be passed from the Host CPU to MIDATA[15:8].
This signal is driven by CPU Interface.
Internal Module Write byte 2 Command: When active along with *MS#, a
valid data IDATA[23:16] will be passed from the Host CPU to MIDATA[23:16].
This signal is driven by CPU Interface.
Internal Module Write byte 3 Command: When active along with *MS#, a
valid data IDATA[31:24] will be passed from the Host CPU to MIDATA[31:24].
This signal is driven by CPU Interface.
Rev. 3.0, 03/01, page 43 of 390