FIFO Polled Mode Operation [ bit 0 of UFCR is 1, and bits 0, 1, 2, 3 of UIER or all are zero].
Either one or both XMIT and RCVR can be in this operation mode which the user program will
check RCVR and XMIT status via the ULSR as described below:
LSR(0): Will be high whenever the RCVR FIFO contains at least one byte.
LSR(1) - LSR(4): Specifies that errors have occurred, Character error status is handled the same
way as that in the interrupt mode. The IIR is not affected since IER(2)=0.
LSR(5): The XMIT FIFO empty indication.
LSR(6): XMIT FIFO and Shift register empty.
LSR(7): RCVR FIFO error indication.
There is no trigger level reached or time-out condition indicated in the FIFO Polled Mode.
12.9
CAUTION
Set bit3 of UMCR to enable interrupt generation.
Rev. 3.0, 03/01, page 170 of 390