Hitachi H8/3637 Hardware Manual

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H8/3637 Series

H8/3637, H8/3636, H8/3635

Hardware Manual

ADE-602-152

Rev. 1.0

8/1/98

Hitachi, Ltd.

MC-Setsu

Table of Contents

Summary of Contents for Hitachi H8/3637

Page 1 H8/3637 Series H8/3637, H8/3636, H8/3635 Hardware Manual ADE-602-152 Rev. 1.0 8/1/98 Hitachi, Ltd. MC-Setsu...
Page 2 Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document.
Page 3 14-bit PWM, five types of timers, two serial communication interface channels, and an A/D converter. This manual describes the hardware of the H8/3637 Series. For details on the H8/3637 Series instruction set, refer to the H8/300L Series Programming Manual.
Page 4: Table Of Contents
Contents Section 1 Overview ......................Overview..........................Internal Block Diagram ..................... Pin Arrangement and Functions ..................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions......................Section 2 ........................Overview ........................... 2.1.1 Features ........................ 13 2.1.2 Address Space ...................... 14 2.1.3 Register Configuration ..................Register Descriptions......................
Page 5 Memory Map ........................Application Notes......................48 2.9.1 Notes on Data Access................... 2.9.2 Notes on Bit Manipulation ................... 2.9.3 Notes on Use of the EEPMOV Instruction ............56 Section 3 Exception Handling ..................57 Overview..........................57 Reset ..........................57 3.2.1 Overview ......................57 3.2.2 Reset Sequence.....................
Page 6 Watch Mode ........................97 5.4.1 Transition to Watch Mode..................97 5.4.2 Clearing Watch Mode ..................97 5.4.3 Oscillator Settling Time after Watch Mode is Cleared ........97 Subsleep Mode ........................98 5.5.1 Transition to Subsleep Mode................98 5.5.2 Clearing Subsleep Mode ..................98 Subactive Mode .........................
Page 7 8.3.1 Overview ......................128 8.3.2 Register Configuration and Description............... 128 8.3.3 Pin Functions......................133 8.3.4 Pin States ......................135 8.3.5 MOS Input Pull-Up ....................135 Port 5..........................136 8.4.1 Overview ......................136 8.4.2 Register Configuration and Description............... 136 8.4.3 Pin Functions......................138 8.4.4 Pin States ......................
Page 8 8.11.3 Pin Functions......................157 8.11.4 Pin States ......................157 Section 9 Timers ........................ 159 Overview..........................159 Timer A..........................160 9.2.1 Overview ......................160 9.2.2 Register Descriptions.................... 161 9.2.3 Timer Operation ....................163 9.2.4 Timer A Operation States..................164 Timer F ..........................165 9.3.1 Overview ......................
Page 9 10.3.1 Overview ......................220 10.3.2 Register Descriptions.................... 222 10.3.3 Operation ......................239 10.3.4 Operation in Asynchronous Mode................ 244 10.3.5 Operation in Synchronous Mode................252 10.3.6 Multiprocessor Communication Function............260 10.3.7 Interrupts ......................266 10.3.8 Application Notes....................267 Section 11 DTMF Generator ....................
Page 10 Section 13 14-bit Pulse Width Modulator (PWM) ............ 293 13.1 Overview..........................293 13.1.1 Features ........................ 293 13.1.2 Block Diagram...................... 293 13.1.3 Pin Configuration ....................294 13.1.4 Register Configuration ..................294 13.2 Register Descriptions......................294 13.2.1 PWM Control Register (PWCR)................294 13.2.2 PWM Data Registers U and L (PWDRU, PWDRL)..........
Page 11 Appendix D Port States in the Different Processing States ........397 Appendix E Product Line-Up ..................398 Appendix F Package Dimensions .................. 399 viii...
Page 12: Overview
(PWM). The H8/3637 Series includes three models, the H8/3637, H8/3636, and H8/3635, with different amounts of on-chip memory: the H8/3637 has 60 kbytes of ROM and 2 kbytes of RAM; the H8/3636 has 48 kbytes of ROM and 2 kbytes of RAM; and the H8/3635 has 40 kbytes of ROM and 2 kbytes of RAM.
Page 13 Table 1.1 Features Item Description High-speed H8/300L CPU • General-register architecture  General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) • Operating speed  Max. operating speed: 5 MHz  Add/subtract: 0.4 µs (operating at ø= 5 MHz) ...
Page 14 Table 1.1 Features (cont) Item Description Memory Large on-chip memory • H8/3637: 60-kbyte ROM, 2-kbyte RAM • H8/3636: 48-kbyte ROM, 2-kbyte RAM • H8/3635: 40-kbyte ROM, 2-kbyte RAM I/O ports 66 I/O ports • I/O pins: 61 • Input pins: 5...
Page 15 Table 1.1 Features (cont) Item Description A/D converter 8-bit successive-approximations A/D converter using a resistance ladder • 4-channel analog input port • Conversion time: 31/ø, 62/ø or 124/ø per channel DTMF generator Built-in tone dialer supporting OSC clock frequencies from 1.2 MHz to 10 MHz in 400-kHz steps 14-bit PWM Pulse-division PWM to reduce ripple...
Page 16: Internal Block Diagram
Internal Block Diagram Figure 1.1 shows a block diagram of the H8/3637 Series. CPU (8-bit) /TMOW Data bus (lower) /TMOFL /TMOFH /TMIG /PWM /IRQ1 /IRQ2/TMCIY (40 k/48 k/ /IRQ3/TMIF (2 kbytes) 60 kbytes) /IRQ4/ADTRG /SCK1 /SI1 /SO1 /SCK3 Timer A...
Page 17: Pin Arrangement And Functions
Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/3637 Series pin arrangement is shown in figure 1.2 and 1.3. 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 /WKP...
Page 18 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 /WKP /WKP /WKP /WKP /WKP /WKP /WKP /WKP TONED /TMOW /TMOFL 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Figure 1.3 Pin Arrangement (FP-80B: Top View)
Page 19: Pin Functions
1.3.2 Pin Functions Table 1.2 outlines the pin functions. Table 1.2 Pin Functions Pin No. TFP-80F Type Symbol TFP-80C FP-80B Name and Functions Power 7, 26 9, 28 Input Power supply: All V pins should be source pins connected to the system power supply (+5 V) 3, 25 5, 27...
Page 20 Table 1.2 Pin Functions (cont) Pin No. TFP-80F Type Symbol TFP-80C FP-80B Name and Functions Interrupt Input External interrupt request 0 to 4: pins These are input pins for external interrupts for which there is a choice between rising and falling edge sensing 38 to 31 40 to 33 Input...
Page 21 Table 1.2 Pin Functions (cont) Pin No. TFP-80F Type Symbol TFP-80C FP-80B Name and Functions I/O ports 76 to 79 78 to 80, Input Port B: This is a 4-bit input port 27 to 30 29 to 32 Port A: This is a 4-bit I/O port. Input or output can be designated for each bit by means of port control register A (PCRA).
Page 22 Table 1.2 Pin Functions (cont) Pin No. TFP-80F Type Symbol TFP-80C FP-80B Name and Functions Serial com- Input SCI1 receive data input: This is the munication SCI1 data input pin interface Output SCI1 send data output: This is the SCI1 (SCI) data output pin SCI1 clock I/O :This is the SCI1 clock...
Page 23: Cpu
Section 2 CPU Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise, optimized instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. •...
Page 24: Address Space
2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
Page 25: Register Descriptions
Register Descriptions 2.2.1 General Registers All the general registers have the same functions, and can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
Page 26 (2) Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions).
Page 27: Initial Register Values
2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized.
Page 28: Data Formats In General Registers
2.3.1 Data Formats in General Registers General register data formats are shown in figure 2.3. Data Type Register No. Data Format 1-bit data Don’t care 1-bit data Don’t care Byte data Don’t care Byte data Don’t care Word data 4-bit BCD data Upper digit Lower digit Don’t care...
Page 29: Memory Data Formats
2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, the access is performed at the preceding even address.
Page 30: Addressing Modes
Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes Address Modes Symbol Register direct Register indirect Register indirect with displacement @(d:16, Rn) Register indirect with post-increment @Rn+...
Page 31 4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand.
Page 32: Effective Address Calculation
8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is H'0000 to H'00FF (0 to 255).
Page 33 Table 2.2 Effective Address Calculation Addressing Mode and Effective Address Instruction Format Calculation Method Effective Address (EA) Register direct, Rn Operand is contents of registers indicated by rm/rn Register indirect, @Rn Contents (16 bits) of register indicated by rm Register indirect with displacement, @(d:16, Rn) Contents (16 bits) of register indicated by rm...
Page 34 Table 2.2 Effective Address Calculation (cont) Addressing Mode and Effective Address Instruction Format Calculation Method Effective Address (EA) Absolute address @aa:8 H'FF @aa:16 Immediate Operand is 1- or 2-byte #xx:8 immediate data #xx:16 Program-counter relative PC contents @(d:8, PC) Sign disp extension disp...
Page 35 Table 2.2 Effective Address Calculation (cont) Addressing Mode and Effective Address Instruction Format Calculation Method Effective Address (EA) Memory indirect, @@aa:8 H'00 Memory contents (16 bits) Legend: rm, rn: Register field Operation field disp: Displacement IMM: Immediate data abs: Absolute address...
Page 36: Instruction Set
Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Instruction Set Function Instructions Number Data transfer MOV, PUSH , POP Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG Logic operations AND, OR, XOR, NOT...
Page 37 Notation General register (destination) General register (source) General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer #IMM...
Page 38: Data Transfer Instructions
2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Page 39 Rm→Rn @Rm←→Rn @(d:16, Rm)←→Rn disp @Rm+→Rn, or Rn →@–Rm @aa:8←→Rn @aa:16←→Rn #xx:8→Rn #xx:16→Rn PUSH, POP → @SP+ Rn, or → @–SP Legend: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 Data Transfer Instruction Codes...
Page 40: Arithmetic Operations
2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Instruction Size* Function Rd ± Rs → Rd, Rd + #IMM → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register.
Page 41: Logic Operations
2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data Rd ∨...
Page 42 Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT MULXU, DIVXU ADD, ADDX, SUBX, CMP (#XX:8) AND, OR, XOR (Rm) AND, OR, XOR (#xx:8) SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Legend:...
Page 43: Bit Manipulations
2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 44 Table 2.8 Bit-Manipulation Instructions (cont) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. C ⊕ [~(<bit-No.> of <EAd>)] → C BIXOR XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag.
Page 45 BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: register direct (Rm) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Operand:...
Page 46 BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Legend: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont)
Page 47: Branching Instructions
2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Function — Branches to the designated address if the specified condition is true. The branching conditions are given below. Mnemonic Description Condition...
Page 48 disp JMP (@Rm) JMP (@aa:16) JMP (@@aa:8) disp JSR (@Rm) JSR (@aa:16) JSR (@@aa:8) Legend: Operation field Condition field Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes...
Page 49: System Control Instructions
2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Instruction Size* Function — Returns from an exception-handling routine SLEEP — Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details Rs →...
Page 50: Block Data Transfer Instruction
RTE, SLEEP, NOP LDC, STC (Rn) ANDC, ORC, XORC, LDC (#xx:8) Legend: Operation field Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction Instruction Size...
Page 51 Legend: Operation field Figure 2.10 Block Data Transfer Instruction Code...
Page 52: Basic Operational Timing
Basic Operational Timing CPU operation is synchronized by a system clock (ø) or a subclock (ø ). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
Page 53: Access To On-Chip Peripheral Modules
2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used.
Page 54: Cpu States
Bus cycle state state state ø or ø Internal Address address bus Internal read signal Internal Read data data bus (read access) Internal write signal Internal data bus Write data (write access) Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) CPU States 2.7.1 Overview...
Page 55 CPU state Reset state The CPU is initialized. Program Active execution state (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode...
Page 56: Program Execution State
Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Exception- Exception- occurs handling handling request complete Program halt state Program execution state SLEEP instruction executed Figure 2.15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode.
Page 57: Memory Map
Memory Map Figure 2.16 shows a memory map for the H8/3637 Series. H8/3635 H8/3636 H8/3637 H'0000 Interrupt vectors (42 bytes) H'0029 H'002A 40 kbytes 48 kbytes On-chip ROM 60 kbytes H'9FFF H'BFFF H'EDFF Reserved H'F77F H'F780 On-chip RAM 2 kbytes...
Page 58: Application Notes
Application Notes 2.9.1 Notes on Data Access Access to Empty Area: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur.
Page 59 Access States H8/3635 H8/3636 H8/3637 Word Byte H'0000 Interrupt vectors (42 bytes) H'0029 H'002A On-chip ROM H'9FFF H'BFFF H'EDFF — — — Reserved H'F77F H'F780 On-chip RAM H'FF7F H'FF80 — — — Reserved H'FF8F H'FF90 Internal I/O registers × 2 or 3...
Page 60: Notes On Bit Manipulation
2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an I/O.
Page 61 Example 2: Here a BSET instruction is executed designating port 6. and P6 are designated as input pins, with a low-level signal input at P6 and a high-level signal at P6 . The remaining pins, P6 to P6 , are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P6 to high-level output.
Page 62 To avoid this problem, store a copy of the PDR6 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR6. [A: Prior to executing BSET] MOV. B #80, The PDR6 value (H'80) is written to a work area in MOV.
Page 63 Bit Manipulation in a Register Containing a Write-only Bit Example 3: In this example, the port 6 control register PCR6 is accessed by a BCLR instruction. As in the examples above, P6 and P6 are input pins, with a low-level signal input at P6 and a high-level signal at P6 .
Page 64 To avoid this problem, store a copy of the PCR6 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR6. [A: Prior to executing BCLR] MOV. B The PCR6 value (H'3F) is written to a work area in MOV.
Page 65 Table 2.12 lists the registers with shared addresses. Table 2.13 lists the registers that contain write- only bits. Table 2.12 Registers with Shared Addresses Register Name Abbreviation Address Timer counter YH / timer load register YH TCYH/TLYH H'FFCE Timer counter YL / timer load register YL TCYL/TLYL H'FFCF Port data register 1*...
Page 66: Notes On Use Of The Eepmov Instruction
2.9.3 Notes on Use of the EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 → ←...
Page 67: Exception Handling
3.2.2 Reset Sequence As soon as the RES pin goes low, all processing is stopped and the H8/3637 Series enters the reset state. To make sure the chip is reset properly, observe the following precautions.
Page 68: Interrupt Immediately After Reset
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after which the program starts executing from the address indicated in PC. When system power is turned on or off, the RES pin should be held low. Figure 3.1 shows the reset sequence.
Page 69: Interrupts
Interrupts 3.3.1 Overview The interrupt sources include 13 external interrupts (WKP to WKP , IRQ to IRQ ), and 17 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed.
Page 70 Table 3.2 Interrupt Sources and Priorities Interrupt Source Interrupt Vector Number Vector Address Priority Reset H'0000 to H'0001 High H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 SCI1 SCI1 transfer complete H'0014 to H'0015 Timer A Timer A overflow...
Page 71: Interrupt Control Registers
3.3.2 Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Name Abbreviation Initial Value Address Interrupt edge select register IEGR H'60 H'FFF2 Interrupt enable register 1 IENR1 H'00 H'FFF3 Interrupt enable register 2 IENR2 H'01 H'FFF4...
Page 72 Edge Select(IEG3): Bit 3 selects the input sensing of pin IRQ Bit 3—IRQ /TMIF. Bit 3: IEG3 Description Falling edge of IRQ /TMIF pin input is detected (initial value) Rising edge of IRQ /TMIF pin input is detected Edge Select(IEG2): Bit 2 selects the input sensing of pin IRQ Bit 2—IRQ /TMCIY.
Page 73 Interrupt Enable Register 1 (IENR1) IENR1 is an 8-bit read/write register that enables or disables interrupt requests. IENTA IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0 Initial value Read/Write Bit 7—Timer A Interrupt Enable (IENTA): Bit 7 enables or disables timer A overflow interrupt requests.
Page 74 Interrupt Enable Register 2 (IENR2) IENDT IENAD — IENTG IENTFH IENTFL IENTY — Initial value Read/Write — — IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7—Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer interrupt requests.
Page 75 Bit 2—Timer FL Interrupt Enable (IENTFL): Bit 2 enables or disables timer FL compare match and overflow interrupt requests. Bit 2: IENTFL Description Disables timer FL interrupts (initial value) Enables timer FL interrupts Bit 1—Timer Y Interrupt Enable (IENTY): Bit 1 enables or disables timer Y overflow interrupt requests.
Page 76 Bit 6—SCI1 Interrupt Request Flag (IRRS1) Bit 6: IRRS1 Description [Clearing conditions] (initial value) When IRRS1 = 1, it is cleared by writing 0 [Setting conditions] When an SCI1 transfer is completed Bit 5—Reserved Bit: Bit 5 is reserved; it is always read as 1, and cannot be modified. Bits 4 to 0—IRQ to IRQ Interrupt Request Flags (IRRI4 to IRRI0)
Page 77 Bit 7—Direct Transfer Interrupt Request Flag (IRRDT) Bit 7: IRRDT Description [Clearing conditions] (initial value) When IRRDT = 1, it is cleared by writing 0 [Setting conditions] When DTON = 1 and a direct transfer is made immediately after a SLEEP instruction is executed Bit 6—A/D Converter Interrupt Request Flag (IRRAD) Bit 6: IRRAD...
Page 78 Bit 2—Timer FL Interrupt Request Flag (IRRTFL) Bit 2: IRRTFL Description [Clearing conditions] (initial value) When IRRTFL = 1, it is cleared by writing 0 [Setting conditions] When counter FL matches output compare register FL in 8-bit timer mode Bit 1—Timer Y Interrupt Request Flag (IRRTY) Bit 1: IRRTY Description [Clearing conditions]...
Page 79 Bits 7 to 0—Wakeup Interrupt Request Flags (IWPF7 to IWPF0) Bits 7 to 0: IWPF7 to IWPF0 Description [Clearing conditions] (initial value) When IWPFn = 1, it is cleared by writing 0 to IWPFn. [Setting conditions] IWPFn is set when pin WKP is set to wakeup interrupt input, and a falling edge input is detected at the pin.
Page 80: External Interrupts
3.3.4 Internal Interrupts There are 17 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2 to 0.
Page 81 3. From among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (Refer to table 3.2 for a list of interrupt priorities.) 4. The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is accepted;...
Page 82 Program execution state IRRI0 = 1 IEN0 = 1 IRRI1 = 1 IEN1 = 1 IRRI2 = 1 IEN2 = 1 IRRDT = 1 IENDT = 1 I = 0 PC contents saved CCR contents saved I ← 1 Branch to interrupt handling routine Legend: Program counter...
Page 83 SP – 4 SP (R7) SP – 3 SP + 1 CCR* SP – 2 SP + 2 SP – 1 SP + 3 SP (R7) SP + 4 Even address Stack area Prior to start of interrupt After completion of interrupt PC and CCR exception handling exception handling...
Page 84 Figure 3.5 Interrupt Sequence...
Page 85: Interrupt Response Time
3.3.6 Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction* 1 to 13 15 to 27 Saving of PC and CCR to stack...
Page 86: Application Notes
Notes on Stack Area Use When word data is accessed in the H8/3637 Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address.
Page 87 When an external interrupt pin function is switched by rewriting the port mode register that to IRQ , and WKP to WKP controls these pins (IRQ ), the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to 0 after switching pin functions.
Page 88 Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0.
Page 89: Clock Pulse Generators
Section 4 Clock Pulse Generators Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Page 90 Connecting a Crystal Oscillator: Figure 4.2 shows a typical method of connecting a crystal oscillator. Ω ±20% R = 1 M C = C = 12 pF ±20% Figure 4.2 Typical Connection to Crystal Oscillator Figure 4.3 shows the equivalent circuit of a crystal oscillator. An oscillator having the characteristics given in table 4.1 should be used.
Page 91 Connecting a Ceramic Oscillator: Figure 4.4 shows a typical method of connecting a ceramic oscillator. = 1 MΩ ± 20% = 30 pF ± 10% = 30 pF ± 10% Ceramic oscillator: Murata Figure 4.4 Typical Connection to Ceramic Oscillator Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points.
Page 92 External Clock Input Method: Connect an external clock signal to pin OSC , and leave pin open. Figure 4.6 shows a typical connection. External clock input Open Figure 4.6 External Clock Input (Example) Frequency Oscillator Clock (ø Duty cycle 45% to 55%...
Page 93: Subclock Generator
Subclock Generator Connecting a 32.768-kHz Crystal Oscillator: Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal oscillator, as shown in figure 4.7. Follow the same precautions as noted in 4.2, Notes on Board Design. C = C = 15 pF (typ.) = 10 MΩ...
Page 94: Prescalers
Prescalers The H8/3637 Series is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules.
Page 95 TEST (VSS) Figure 4.10 Example of Crystal and Ceramic Oscillator Layout.
Page 96: Power-Down Modes
Section 5 Power-Down Modes Overview The H8/3637 Series has seven modes of operation after a reset. These include six power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the seven operation modes. Table 5.1...
Page 97 Program executing Program execution stopped Reset state LSON = 0, MSON = 0 Program execution stopped Active (high-speed) mode SSBY = 1, TMA3 = 0, SSBY = 0, LSON = 0 LSON = 0 Standby mode Sleep mode LSON = 0, MSON = 1 Active (medium-speed)
Page 98 Table 5.2 Internal State in Each Operation Mode Active Mode Function High Medium Sleep Watch Subactive Subsleep Standby Speed Speed Mode Mode Mode Mode Mode System clock oscillator Functional Functional Functional Stopped Stopped Stopped Stopped Subclock oscillator Functional Functional Functional Functional Functional Functional Functional Instructions Functional Functional Stopped Stopped Functional Stopped...
Page 99: System Control Registers
5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5.3. Table 5.3 System Control Register Name Abbreviation Initial Value Address System control register 1 SYSCR1 H'07 H'FFF0 System control register 2 SYSCR2 H'E0 H'FFF1 System Control Register 1 (SYSCR1)
Page 100 Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description Wait time = 8,192 states (initial value) Wait time = 16,384 states Wait time = 32,768 states Wait time = 65,536 states Wait time = 131,072 states Note: * Don’t care Bit 3—Low Speed on Flag (LSON): This bit chooses the system clock (ø) or subclock (ø...
Page 101 Bit 4— Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency at which the watch clock signal (ø ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (ø ) generated by the system clock pulse generator. When ø to 10 MHz, clear NESEL to 0.
Page 102: Sleep Mode
Bits 1 and 0—Subactive Mode Clock Select (SA1 and SA0): These bits select the CPU clock rate (ø /2, ø /4, or ø /8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1: SA1 Bit 0: SA0 Description ø...
Page 103: Standby Mode
Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared to 0, and bit TMA3 in timer mode register A (TMA) is cleared to 0.
Page 104: Oscillator Settling Time After Standby Mode Is Cleared
5.3.3 Oscillator Settling Time after Standby Mode is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. When a Crystal Oscillator is Used: Table 5.4 gives settings for various operating frequencies. Set bits STS2 to STS0 for a waiting time of at least 10 ms. Table 5.4 Clock Frequency and Settling Time (times are in ms) STS2...
Page 105: Transition To Standby Mode And Pin States
5.3.4 Transition to Standby Mode and Pin States The system goes from active (high-speed) mode or active (medium-speed) mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0. At the same time, pins go to the high-impedance state (except pins with MOS pull-up turned on).
Page 106: Watch Mode
Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules other than timer A is halted.
Page 107: Subsleep Mode
Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON is set to 1, and bit TMA3 in TMA is set to 1.
Page 108: Subactive Mode
Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, IRQ , or WKP to WKP interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer G, IRQ to IRQ , or WKP...
Page 109: Active (Medium-Speed) Mode
Active (medium-speed) Mode 5.7.1 Transition to Active (medium-speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ , IRQ , or WKP to WKP interrupts in standby...
Page 110: Direct Transfer
Direct Transfer 5.8.1 Overview The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1.
Page 111: Direct Transfer Time
(number of internal processing states) } × (t before transition) + (number of interrupt exception handling execution states) × after transition) ..............(1) Example: H8/3637 Series direct transfer time = (2 + 1) × 2t + 14 × 16t = 230t Legend: : OSC clock cycle time : System clock (ø) cycle time...
Page 112 { (standby time set in STS2 to STS0) + (number of interrupt exception handling execution states) } × after transition) ..............(3) Example: H8/3637 Series direct transfer time = (2 + 1) × 8t + (8192 + 14) × 2t = 24t 16412t (When ø...
Page 113: Rom
Section 6 ROM Overview The H8/3637 has 60 kbytes of on-chip mask ROM, while the H8/3636 has 48 kbytes and the H8/3635 has 40 kbytes. The H8/3637 also has 60 kbytes of on-chip PROM. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data.
Page 114: Prom Mode
PROM Mode 6.2.1 Selection of PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcomputer and allows the on-chip PROM to be programmed in the same way as the HN27C101, except that page programming is not supported. Table 6.1 shows how to set PROM mode.
Page 115 H8/3637 EPROM socket TFP-80C HN27C101 FP-80B (32 pins) TFP-80F 9, 28 7, 26 TEST 5, 27 3, 25 Note: Pins not indicated in the figure should be left open. Figure 6.2 Socket Adapter Pin Correspondence...
Page 116 Address in Address in MCU mode PROM mode H'0000 H'0000 On-chip PROM H'EDFF H'EDFF Unused area H'1FFFF Note: * Unpredictable data may be output if this area is read in PROM mode. When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF.
Page 117: Programming
Programming The program, verify, and other modes are selected as shown in table 6.2 in PROM mode. Table 6.2 Mode Selection in PROM Mode Mode to EO to EA Write Data input Address input Verify Data output Address input Programming High impedance Address input disabled Legend:...
Page 118: Programming And Verification
6.3.1 Programming and Verification An efficient, high-speed, high-reliability programming procedure can be used to program and verify data. This procedure programs the chip quickly without subjecting it to voltage stress and without sacrificing data reliability. Data in unused address areas is H'FF. Figure 6.4 shows the basic high-speed, high-reliability programming flow chart.
Page 119 Table 6.3 and table 6.4 give the electrical characteristics in programming mode. Table 6.3 DC Characteristics = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 25°C ±5°C) (Conditions: V = 0 V, T Test Item Symbol Unit Condition Input high-...
Page 120 Table 6.4 AC Characteristics = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, T = 25°C ±5°C) (Conditions: V Test Item Symbol Unit Conditions µs Address setup time — — Figure 6.5* µs OE setup time — — µs Data setup time —...
Page 121 Figure 6.5 shows a program/verify timing diagram. Program Verify Address Data Input data Output data Note: * t is defined by the value given in the high-speed, high-reliability programming flow chart in figure 6.4. Figure 6.5 PROM Program/Verify Timing...
Page 122: Programming Precautions
) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C101 will result in correct V of 12.5 V.
Page 123: Reliability Of Programmed Data
If write errors occur repeatedly while the same PROM programmer is being used, stop programming and check for problems in the PROM programmer and socket adapter, etc. Please notify your Hitachi representative of any problems occurring during programming or in screening after high-temperature baking.
Page 124: Ram
Section 7 RAM Overview The H8/3637 Series has 2 kbytes of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 Block Diagram Figure 7.1 shows a block diagram of the on-chip RAM.
Page 125: I/O Ports
Section 8 I/O Ports Overview The H8/3637 Series is provided with six 8-bit I/O ports, one 7-bit I/O port, one 4-bit I/O port, one 2-bit I/O port, one 4-bit input-only port, and one 1-bit input-only port. Table 8.1 indicates the functions of each port.
Page 126 Table 8.1 Port Functions Function Switching Port Description Pins Other Functions Register • 8-bit I/O port Port 1 to P1 External interrupts 3 to 1 PMR1 to IRQ • Input pull-up MOS Timer event input TMIF, TMCIY TCRF, TMY TMIF, TMCIY option /PWM 14-bit PWM output...
Page 127: Port 1
Port 1 8.2.1 Overview Port 1 is an 8-bit I/O port. Figure 8.1 shows its pin configuration. /IRQ /TMIF /IRQ /TMCIY /IRQ /PWM Port 1 /TMIG /TMOFH /TMOFL /TMOW Figure 8.1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration.
Page 128 Port Data Register 1 (PDR1) Initial value Read/Write PDR1 is an 8-bit register that stores data for pins P1 to P1 of port 1. If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are directly read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
Page 129 Port Mode Register 1 (PMR1) IRQ3 IRQ2 IRQ1 TMIG TMOFH TMOFL TMOW Initial value Read/Write PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'00. Bit 7—P1 /IRQ /TMIF Pin Function Switch (IRQ3): This bit selects whether pin or as IRQ...
Page 130 Bit 4—P1 /PWM Pin Function Switch (PWM): This bits selects whether the P1 /PWM pin is used as P1 or as PWM. Bit 4: PWM Description Functions as P1 I/O pin (initial value) Functions as PWM output pin Bit 3—P1 /TMIG Pin Function Switch (TMIG): This bit selects whether pin P1 /TMIG is used as P1...
Page 131: Pin Functions
8.2.3 Pin Functions Table 8.3 shows the port 1 pin functions. Table 8.3 Port 1 Pin Functions Pin Functions and Selection Method /IRQ /TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR1 in PCR1.
Page 132 Table 8.3 Port 1 Pin Functions (cont) Pin Functions and Selection Method /TMIG The pin function depends on bit TMIG in PMR1 and bit PCR1 in PCR1. TMIG PCR1 Pin function input pin output pin TMIG input pin /TMOFH The pin function depends on bit TMOFH in PMR1 and bit PCR1 in PCR1.
Page 133: Pin States
8.2.4 Pin States Table 8.4 shows the port 1 pin states in each operating mode. Table 8.4 Port 1 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /IRQ /TMIF High- Retains Retains High- Retains Functional Functional impedance previous previous impedance* previous...
Page 134: Port 5
Port 2 8.3.1 Overview Port 2 is an 7-bit I/O port and 1-bit input port. Figure 8.2 shows its pin configuration. /IRQ /TXD /RXD /SCK Port 2 /SCK /IRQ /ADTRG Figure 8.2 Port 2 Pin Configuration 8.3.2 Register Configuration and Description Table 8.5 shows the port 2 register configuration.
Page 135 Port Data Register 2 (PDR2) Initial value Read/Write PDR2 is an 8-bit register that stores data for pins P2 to P2 of port 2. If port 2 is read while PCR2 bits are set to 1, the values stored in PDR2 are directly read, regardless of the actual pin states. If port 2 is read while PCR2 bits are cleared to 0, the pin states are read.
Page 136 Port Mode Register 2 (PMR2) IRQ0 — POF1 SCK1 IRQ4 Initial value Read/Write — PMR2 is an 8-bit read/write register for controlling the selection of pin functions for pins P2 and P2 , controlling the PMOS on/off option for pin P2 , and controlling the TMIG input noise canceller.
Page 137 Bit 3—P2 Pin Function Switch (SO1): This bit selects whether pin P2 is used as P2 or as SO Bit 3: SO1 Description Functions as P2 I/O pin (initial value) Functions as SO output pin Bit 2—P2 Pin Function Switch (SI1): This bit selects whether pin P2 is used as P2 as SI Bit 2: SI1...
Page 138 Port Mode Register 6 (PMR6) — — — — — — — Initial value Read/Write — — — — Bits 7, 6, 5, and 3: Reserved Bits: Bits 7, 6, 5, and 3 are reserved bits. They are always read as 1 and cannot be modified.
Page 139: Pin Functions
8.3.3 Pin Functions Table 8.6 shows the port 2 pin functions. Table 8.6 Port 2 Pin Functions Pin Functions and Selection Method /IRQ The pin function depends on bit IRQ0 in PMR2 and bit PCR2 in PCR2. IRQ0 PCR2 Pin function input pin High- input pin...
Page 140 Table 8.6 Port 2 Pin Functions (cont) Pin Functions and Selection Method The pin function depends on bit SI1 in PMR2 and bit PCR2 in PCR2. PCR2 Pin function input pin output pin input pin /SCK The pin function depends on bit SCK1 in PMR2, bit CKS3 in SCR1, and bit PCR2 in PCR2.
Page 141 8.3.4 Pin States Table 8.7 shows the port 2 pin states in each operating mode. Table 8.7 Port 2 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /IRQ High- High- High- High- High- High- High- impedance impedance impedance impedance impedance impedance...
Page 142: Overview
Port 5 8.4.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8.3. P5 /WKP P5 /WKP P5 /WKP P5 /WKP Port 5 P5 /WKP P5 /WKP P5 /WKP P5 /WKP Figure 8.3 Port 5 Pin Configuration 8.4.2 Register Configuration and Description Table 8.8 shows the port 5 register configuration.
Page 143 Port Data Register 5 (PDR5) Initial value Read/Write PDR5 is an 8-bit register that stores data for port 5 pins P5 to P5 . If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are directly read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
Page 144: Pin Functions
Port Mode Register 5 (PMR5) Initial value Read/Write PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit n: P5 /WKP Pin Function Switch (WKPn): This bit selects whether it is used as P5 or as Bit n: WKPn Description...
Page 145: Pin States
8.4.4 Pin States Table 8.10 shows the port 5 pin states in each operating mode. Table 8.10 Port 5 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /WKP High- Retains Retains High- Retains Functional Functional to P5 /WKP impedance previous previous...
Page 146: Port 8
Port 6 8.5.1 Overview Port 6 is an 8-bit I/O port, configured as shown in figure 8.4. Port 6 Figure 8.4 Port 6 Pin Configuration 8.5.2 Register Configuration and Description Table 8.11 shows the port 6 register configuration. Table 8.11 Port 6 Registers Name Abbrev.
Page 147 Port Data Register 6 (PDR6) Initial value Read/Write PDR6 is an 8-bit register that stores data for port 6 pins P6 to P6 . If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are directly read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read.
Page 148: Pin Functions
8.5.3 Pin Functions Table 8.12 shows the port 6 pin functions. Table 8.12 Port 6 Pin Functions Pin Functions and Selection Method to P6 The pin function depends on bit PCR6 in PCR6. (n = 7 to 0) PCR6 Pin function input pin output pin 8.5.4...
Page 149 Port 7 8.6.1 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8.5. Port 7 Figure 8.5 Port 7 Pin Configuration 8.6.2 Register Configuration and Description Table 8.14 shows the port 7 register configuration. Table 8.14 Port 7 Registers Name Abbrev.
Page 150 Port Data Register 7 (PDR7) Initial value Read/Write PDR7 is an 8-bit register that stores data for port 7 pins P7 to P7 . If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are directly read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read.
Page 151 8.6.3 Pin Functions Table 8.15 shows the port 7 pin functions. Table 8.15 Port 7 Pin Functions Pin Functions and Selection Method to P7 The pin function depends on bit PCR7 in PCR7. (n = 7 to 0) PCR7 Pin function input pin output pin 8.6.4...
Page 152 Port 8 8.7.1 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8.6. Port 8 Figure 8.6 Port 8 Pin Configuration 8.7.2 Register Configuration and Description Table 8.17 shows the port 8 register configuration. Table 8.17 Port 8 Registers Name Abbrev.
Page 153 Port Data Register 8 (PDR8) Initial value Read/Write PDR8 is an 8-bit register that stores data for port 8 pins P8 to P8 . If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are directly read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read.
Page 154 8.7.3 Pin Functions Table 8.18 gives the port 8 pin functions. Table 8.18 Port 8 Pin Functions Pin Functions and Selection Method to P8 The pin function depends on bit PCR8 in PCR8. (n = 7 to 0) PCR8 Pin function input pin output pin 8.7.4...
Page 155 Port 9 8.8.1 Overview Port 9 is an 8-bit I/O port configured as shown in figure 8.7. Port 9 Figure 8.7 Port 9 Pin Configuration 8.8.2 Register Configuration and Description Table 8.20 shows the port 9 register configuration. Table 8.20 Port 9 Registers Name Abbrev.
Page 156 Port Data Register 9 (PDR9) Initial value Read/Write PDR9 is an 8-bit register that stores data for port 9 pins P9 to P9 . If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are directly read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read.
Page 157 8.8.3 Pin Functions Table 8.21 gives the port 9 pin functions. Table 8.21 Port 9 Pin Functions Pin Functions and Selection Method to P9 The pin function depends on bit PCR9 in PCR9. (n = 7 to 0) PCR9 Pin function input pin output pin 8.8.4...
Page 158: Port A
Port A 8.9.1 Overview Port A is a 4-bit I/O port configured as shown in figure 8.8. Port A Figure 8.8 Port A Pin Configuration 8.9.2 Register Configuration and Description Table 8.23 shows the port A register configuration. Table 8.23 Port A Registers Name Abbrev.
Page 159 Port Data Register A (PDRA) — — — — Initial value Read/Write — — — — PDRA is an 8-bit register that stores data for port A pins PA to PA . If port A is read while PCRA bits are set to 1, the values stored in PDRA are directly read, regardless of the actual pin states. If port A is read while PCRA bits are cleared to 0, the pin states are read.
Page 160: Pin Functions
8.9.3 Pin Functions Table 8.24 gives the port A pin functions. Table 8.24 Port A Pin Functions Pin Functions and Selection Method to PA The pin function depends on bit PCRA in PCRA. (n = 3 to 0) PCRA Pin function input pin output pin 8.9.4...
Page 161: Port B
8.10 Port B 8.10.1 Overview Port B is an 4-bit input-only port configured as shown in figure 8.9. PB /AN PB /AN Port B PB /AN PB /AN Figure 8.9 Port B Pin Configuration 8.10.2 Register Configuration and Description Table 8.26 shows the port B register configuration. Table 8.26 Port B Register Name Abbrev.
Page 162: Overview
8.11 Port E 8.11.1 Overview Port E is a 2-bit I/O port, configured as shown in figure 8.10. Port E Figure 8.10 Port E Pin Configuration 8.11.2 Register Configuration and Description Table 8.27 shows the port E register configuration. Table 8.27 Port E Registers Name Abbrev.
Page 163 Port Control Register E (PCRE) — — — — PCRE PCRE — — Initial value Read/Write — — — — — — PCRE is a 2-bit register for controlling whether each of the port E pins PE and PE functions as an input pin or output pin.
Page 164: Timers
Section 9 Timers Overview The H8/3637 Series provides five timers (timers A, F, G, Y, and watchdog timer) on-chip. Table 9.1 outlines the functions of timers A, F, G, Y, and watchdog timer. Table 9.1 Timer Functions Event Waveform Name...
Page 165: Timer A
Timer A 9.2.1 Overview Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz or from the system clock can be output at the TMOW pin. Features: Features of timer A are given below.
Page 166: Register Descriptions
Pin Configuration: Table 9.2 shows the timer A pin configuration. Table 9.2 Pin Configuration Name Abbrev. Function Clock output TMOW Output Output of waveform generated by timer A output circuit Register Configuration: Table 9.3 shows the register configuration of timer A. Table 9.3 Timer A Registers Name...
Page 167 Bit 7: TMA7 Bit 6: TMA6 Bit 5: TMA5 Clock Output ø/32 (initial value) ø/16 ø/8 ø/4 ø ø ø ø Bit 4—Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0—Internal Clock Select (TMA3 to TMA0): Bits 3 to 0 select the clock input to TCA. The selection is made as follows.
Page 168: Timer Operation
Timer Counter A (TCA) TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA).
Page 169: Timer A Operation States
Clock Output: Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin TMOW. Eight different clock output signals can be selected by means of bits TMA7 to TMA5 in TMA. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode.
Page 170: Timer F
Timer F 9.3.1 Overview Timer F is a 16-bit timer with an output compare function. Compare match signals can be used to reset the counter, request an interrupt, or toggle the output. Timer F can also be used for external event counting, and can operate as two independent 8-bit timers, timer FH and timer FL.
Page 171 Block Diagram: Figure 9.2 shows a block diagram of timer F. ø IRRTFL TCRF TCFL TMIF Toggle TMOFL Compare circuit circuit OCRFL TCFH Toggle TMOFH Match Compare circuit circuit OCRFH TCSRF IRRTFH Legend: TCRF: Timer control register F TCSRF: Timer control status register F TCFH: 8-bit timer counter FH TCFL:...
Page 172: Register Descriptions
Pin Configuration: Table 9.5 shows the timer F pin configuration. Table 9.5 Pin Configuration Name Abbrev. Function Timer F event input TMIF Input Event input to TCFL Timer FH output TMOFH Output Timer FH toggle output Timer FL output TMOFL Output Timer FL toggle output Register Configuration: Table 9.6 shows the register configuration of timer F.
Page 173 TCFH and TCFL can be read and written by the CPU, but in 16-bit mode, data transfer with the CPU takes place via a temporary register (TEMP). For details see 9.3.3, Interface with the CPU. Upon reset, TCFH and TCFL are each initialized to H'00. 16-Bit Mode (TCF): 16-bit mode is selected by clearing bit CKSH2 to 0 in timer control register F (TCRF).
Page 174 upper 8 bits and OCRFL as the lower 8 bits of the register, or OCRFH and OCRFL can be used as independent 8-bit registers. OCRFH and OCRFL can be read and written by the CPU, but in 16-bit mode, data transfer with the CPU takes place via a temporary register (TEMP).
Page 175 Timer Control Register F (TCRF) TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value Read/Write TCRF is an 8-bit write-only register. It is used to switch between 16-bit mode and 8-bit mode, to select among four internal clocks and an external event, and to select the output level at pins TMOFH and TMOFL.
Page 176 Bits 2 to 0—Clock Select L (CKSL2 to CKSL0): Bits 2 to 0 select the input to TCFL from four internal clock signals or external event input. Bit 2: CKSL2 Bit 1: CKSL1 Bit 0: CKSL0 Description External event (TMIF). Rising or falling edge is counted (see note).
Page 177 Bit 6—Compare Match Flag H (CMFH): Bit 6 is a status flag indicating a compare match between TCFH and OCRFH. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6: CMFH Description [Clearing conditions] (initial value) After reading CMFH = 1, cleared by writing 0 to CMFH...
Page 178 Bit 2—Compare Match Flag L (CMFL): Bit 2 is a status flag indicating a compare match between TCFL and OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2: CMFL Description [Clearing conditions] (initial value) After reading CMFL = 1, cleared by writing 0 to CMFL...
Page 179: Interface With The Cpu
9.3.3 Interface with the CPU TCF and OCRF are 16-bit read/write registers, whereas the data bus between the CPU and on-chip peripheral modules has an 8-bit width. For this reason, when the CPU accesses TCF or OCRF, it makes use of an 8-bit temporary register (TEMP). In 16-bit mode, when reading or writing TCF or writing OCRF, always use two consecutive byte size MOV instructions, and always access the upper byte first.
Page 180 When writing the upper byte Internal data bus [H'AA] interface TEMP [H'AA] TCFH TCFL When writing the lower byte Internal data bus [H'55] interface TEMP [H'AA] TCFH TCFL [H'AA] [H'55] Figure 9.3 TCF Write Operation (CPU → TCF)
Page 181 When reading the upper byte Internal data bus interface [H'AA] TEMP (H'FF) TCFH TCFL [H'AA] [H'FF] When reading the lower byte Internal data bus interface [H'FF] TEMP [H'FF] TCFH TCFL [AB] [00] Note: * Becomes H'AB00 if counter is incremented once. Figure 9.4 TCF Read Operation (TCF →...
Page 182: Timer Operation
9.3.4 Timer Operation Timer F is a 16-bit timer/counter that increments with each input clock. When the value set in output compare register F matches the count in timer F, the timer can be cleared, an interrupt can be requested, and the port output can be toggled. Timer F can also be used as two independent 8-bit timers.
Page 183 TCF Count Timing: TCF is incremented by each pulse of the input clock (internal clock or external event). • Internal clock The settings of bits CKSH2 to CKSH0 or bits CKSL2 to CKSL0 in TCRF select one of four internal clock signals (ø/32, ø/16, ø/4, or ø/2) divided from the system clock (ø). •...
Page 184: Application Notes
Compare Match Flag Set Timing: The compare match flags (CMFH or CMFL) are set to 1 when a compare match occurs between TCF and OCRF. A compare match signal is generated in the final state in which the values match (when TCF changes from the matching count value to the next value).
Page 185 8-Bit Timer Mode • TCFH and OCRFH The output at pin TMOFH toggles when there is a compare match. If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new value written in bit TOLH will be output at pin TMOFH.
Page 186: Timer G
Timer G 9.4.1 Overview Timer G is an 8-bit timer, with input capture/interval functions for separately capturing the rising edge and falling edge of pulses input at the input capture pin (input capture input signal). Timer G has a built-in noise canceller circuit that can eliminate high-frequency noise from the input capture signal, enabling accurate measurement of its duty cycle.
Page 187 Block Diagram: Figure 9.6 shows a block diagram of timer G. ø Level sense circuit ø /2 ICRGF Edge Noise sense canceller TMIG circuit circuit ICRGR IRRTG Legend: TMG: Timer mode register G TCG: Timer counter G ICRGF: Input capture register GF ICRGR: Input capture register GR IRRTG:...
Page 188: Register Descriptions
Register Configuration: Table 9.9 shows the register configuration of timer G. Table 9.9 Timer G Registers Name Abbrev. Initial Value Address Timer mode register G H'00 H'FFBC Timer counter G — H'00 — Input capture register GF ICRGF H'00 H'FFBD Input capture register GR ICRGR H'00...
Page 189 Input Capture Register GF (ICRGF) ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value Read/Write ICRGF is an 8-bit read-only register. When the falling edge of the input capture signal is detected, the TCG value at that time is transferred to ICRGF. If the input capture interrupt select bit (IIEGS) is set to 1 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1.
Page 190 Timer Mode Register G (TMG) OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value Read/Write R/W* R/W* Note: * Only 0 can be written, to clear flag. TMG is an 8-bit read/write register. It controls the choice of four internal clocks, counter clear selection, and edge selection for input capture interrupt requests.
Page 191 Bit 4—Input Capture Interrupt Edge Select (IIEGS): Bit 4 selects the input signal edge at which input capture interrupts are requested. Bit 4: IIEGS Description Interrupts are requested at the rising edge of the input capture signal (initial value) Interrupts are requested at the falling edge of the input capture signal Bits 3, 2—Counter Clear 1, 0 (CCLR1, CCLR0): Bits 3 and 2 designate whether TCG is cleared at the rising, falling, or both edges of the input capture signal, or is not cleared.
Page 192: Noise Canceller Circuit
9.4.3 Noise Canceller Circuit The noise canceller circuit built into the H8/3637 Series is a digital low-pass filter that rejects high-frequency pulse noise in the input at the input capture pin. The noise canceller circuit is enabled by the noise canceller select (NCS)* bit in port mode register 2 (PMR2).
Page 193: Timer Operation
Figure 9.8 shows a typical timing diagram for the noise canceller circuit. In this example, a high- level input at the input capture pin is rejected as noise because its pulse width is less than five sampling clock ø cycles. Input capture input signal Sampling...
Page 194 Timer G has a noise canceller circuit that rejects high-frequency pulse noise in the input to pin TMIG. See 9.4.3, Noise Canceller Circuit, for details. Note: * Rewriting the TMIG bit may cause an internal input capture signal to be generated. •...
Page 195 • Timing with noise canceller function enabled When input capture noise cancelling is enabled, the external input capture signal is routed via the noise canceller circuit, so the internal signals are delayed from the input edge by five sampling clock cycles. Figure 9.10 shows the timing. External input capture signal Sampling clock...
Page 196 TCG Clear Timing: TCG can be cleared at the rising edge, falling edge, or both edges of the external input capture signal. Figure 9.12 shows the timing for clearing at both edges. External input capture signal Internal input capture signal F Internal input capture signal R H'00...
Page 197: Application Notes
9.4.5 Application Notes Input Clock Switching and TCG Operation: Depending on when the input clock is switched, there will be cases in which TCG is incremented in the process. Table 9.11 shows the relation between internal clock switchover timing (selected in bits CKS1 and CKS0) and TCG operation. If an internal clock (derived from the system clock ø...
Page 198 Table 9.11 Internal Clock Switching and TCG Operation (cont) Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation Goes from high level Clock before to low level switching Clock after switching Count clock N +1 N +2 CKS bits modified Goes from high level Clock before...
Page 199 Note on Rewriting Port Mode Registers: When a port mode register setting is modified to enable or disable the input capture function or input capture noise canceling function, note the following points. • Switching the function of the input capture pin When the function of the input capture pin is switched by modifying port mode register 1 (PMR1) bit 3 (the TMIG bit), an input capture edge may be recognized even though no valid signal edge has been input.
Page 200 If switching of the pin function generates a false input capture edge matching the edge selected by the input capture interrupt edge select bit (IIEGS), the interrupt request flag will be set to 1, making it necessary to clear this flag to 0 before using the interrupt function. Figure 9.13 shows the procedure for modifying port mode register settings and clearing the interrupt request flag.
Page 201: Sample Timer G Application
9.4.6 Sample Timer G Application The absolute values of the high and low widths of the input capture signal can be measured by using timer G. The CCLR1 and CCLR0 bits of TMG should be set to 1. Figure 9.14 shows an example of this operation.
Page 202 Block Diagram: Figure 9.15 shows a block diagram of timer Y. ø TMCIY IRRTY Legend: TMY: Timer mode register Y TCY: Timer counter Y TLY: Timer load register Y IRRTY: Timer Y overflow interrupt request flag PSS: Prescaler S Figure 9.15 Block Diagram of Timer Y Pin Configuration: Table 9.14 shows the timer Y pin configuration.
Page 203: Register Descriptions
9.5.2 Register Descriptions Timer Mode Register Y (TMY) TMY7 — — — — TMY2 TMY1 TMY0 Initial value Read/Write — — — — Timer mode register Y (TMY) is an 8-bit read/write register that performs auto-reload function selection and input clock selection. Upon reset, TMY is initialized to H'78.
Page 204 Timer Counter Y (TCY) Timer Counter YH (TCYH) Timer Counter YL (TCYL) Initial value Read/Write TCYH TCYL Timer counter Y (TCY) is a 16-bit readable up-counter that is incremented by an input internal clock or external events. The input clock is selected with bits TMY2 to TMY0 in TMY.
Page 205: Interface With The Cpu
Timer Load Register Y (TLY) Timer Load Register YH (TLYH) Timer Load Register YL (TLYL) Initial value Read/Write TLYH TLYL Timer load register Y (TLY) is a 16-bit write-only register that is set with the TCY load value. When the load value is set in TLY, that value is simultaneously loaded into TCY, and TCY starts counting up from that value.
Page 206 When writing the upper byte Module internal data bus interface [H'AA] TEMP [H'AA] TLYH TLYL When writing the lower byte Module internal data bus interface [H'55] TEMP [H'AA] TLYH TLYL [H'AA] [H'55] Figure 9.16 TLY Write Operation (CPU → TLY) Read Access: When the upper byte is read, the upper-byte data is sent directly to the CPU, and the lower byte is loaded into TEMP.
Page 207 When reading the upper byte Module internal data bus interface [H'AA] TEMP [H'FF] TCYH TCYL [H'AA] [H'FF] When reading the lower byte Module internal data bus interface [H'FF] TEMP [H'FF] TCYH TCYL [AB] [00] Note: * Becomes H'AB00 if counter is incremented once. Figure 9.17 TCY Read Operation (TCY →...
Page 208: Operation
9.5.4 Operation Interval Timer Operation: When TMY7 in TMY is cleared to 0, timer Y operates as a 16- bit interval timer. In a reset, TCY is initialized to H'0000 and TMY7 is cleared to 0. Therefore, immediately after a reset, interval timer count-up continues. The timer Y operating clock can be selected with bits TMY2 to TMY0 in TMY from seven internal clocks output from prescaler S and the external clock from the TMCIY input pin.
Page 209: Timer Y Operating Modes
9.5.5 Timer Y Operating Modes Timer Y operating modes are shown in table 9.16. Table 9.16 Timer Y Operating Modes Sub- Sub- Operation Mode Reset Active Sleep Watch active sleep Standby Interval Reset Functions Functions Halted Halted Halted Halted Auto- Reset Functions Functions...
Page 210: Register Descriptions
Block Diagram: Figure 9.18 shows a block diagram of the watchdog timer. TCSRW ø/8192 ø TCSRW Internal reset signal Legend: TCSRW: Timer control/status register W TCW: Timer counter W PSS: Prescaler S Figure 9.18 Block Diagram of Watchdog Timer Register Configuration: Table 9.17 shows the watchdog timer register configuration. Table 9.17 Watchdog Timer Registers Name Abbrev.
Page 211 Timer control/status register W (TCSRW) is an 8-bit read/write register that performs TCSRW and TCW write control and watchdog timer operation control, and indicates the operation status. Bit 7—Bit 6 Write Inhibit (B6WI): Bit 7 controls writing of data to bit 6 of TCSRW. This bit is always read as 1.
Page 212 Bit 3: B2WI Description Writing to bit 2 is enabled Writing to bit 2 is disabled (initial value) Bit 2—Watchdog Timer On (WDON): Bit 2 control watchdog timer operation. The count-up starts when this bit is set to 1, and stops when it is cleared to 0. Bit 2: WDON Description Watchdog timer operation disabled...
Page 213: Operation
Bit 0: WRST Description [Clearing conditions] (initial value) • Reset by RES pin • When 0 is written to WRST while writing 0 to B0WI when TCSRWE is set to 1 [Setting condition] When TCW overflows and an internal reset signal is generated Timer Counter W (TCW) TCW7 TCW6...
Page 214: Watchdog Timer Operating Modes
Example: With 30 ms overflow period when ø = 4 MHz 4 × 10 × 30 × 10 –3 = 14.6 8192 Therefore, 256 – 15 = 241 (H'F1) is set in TCW. TCW overflow H'FF H'F1 TCW count value H'00 Start H'F1 written to TCW...
Page 215: Section 10 Serial Communication Interface
Section 10 Serial Communication Interface 10.1 Overview The H8/3637 Series is provided with a two-channel serial communication interface (SCI), SCI1 and SCI3. Table 10.1 summarizes the functions and features of the two SCI channels. Table 10.1 Serial Communication Interface Functions...
Page 216 Block Diagram: Figure 10.1 shows a block diagram of SCI1. ø SCR1 Transmit/receive SCSR1 control circuit Transfer bit counter SDRU SDRL IRRS1 Legend: SCR1: Serial control register 1 SCSR1: Serial control/status register 1 SDRU: Serial data register U SDRL: Serial data register L IRRS1: SCI1 interrupt request flag PSS:...
Page 217: Register Descriptions
Register Configuration: Table 10.3 shows the SCI1 register configuration. Table 10.3 SCI1 Registers Name Abbrev. Initial Value Address Serial control register 1 SCR1 H'00 H'FFA0 Serial control status register 1 SCSR1 H'9C H'FFA1 Serial data register U SDRU Undefined H'FFA2 Serial data register L SDRL Undefined...
Page 218 Bit 3—Clock Source Select 3 (CKS3): Bit 3 selects the clock source and sets pin SCK as an input or output pin. Bit 3: CKS3 Description Clock source is prescaler S, and pin SCK is output pin (initial value) Clock source is external clock, and pin SCK is input pin Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS 0): When CKS3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle.
Page 219 Bit 6—Extended Data Bit (SOL): Bit 6 sets the SO output level. When read, SOL returns the output level at the SO pin. After completion of a transmission, SO continues to output the value of the last bit of transmitted data. The SO output can be changed by writing to SOL before or after a transmission.
Page 220 Bit 0: STF Description Read Indicates that transfer is stopped (initial value) Write Invalid Read Indicates transfer in progress Write Starts a transfer operation Serial Data Register U (SDRU) SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write SDRU is an 8-bit read/write register.
Page 221: Operation
SDRL must be written or read only after data transmission or reception is complete. If this register is read or written while a data transfer is in progress, the data contents are not guaranteed. The SDRL value upon reset is not fixed. 10.2.3 Operation Data can be sent and received in an 8-bit or 16-bit format, synchronized to an internal or external...
Page 222 5. After data transmission is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1. When an internal clock is used, a serial clock is output from pin SCK in synchronization with the transmit data. After data transmission is complete, the serial clock is not output until the next time the start flag is set to 1.
Page 223: Interrupt Sources
6. Read the received data from SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL When an internal clock is used, a serial clock is output from pin SCK in synchronization with the transmit data.
Page 224: Sci3
10.3 SCI3 10.3.1 Overview Serial communication interface 3 (SCI3) has both synchronous and asynchronous serial data communication capabilities. It also has a multiprocessor communication function for serial data communication among two or more processors. Features: SCI3 features are listed below. •...
Page 225 Block Diagram: Figure 10.3 shows a block diagram of SCI3. External clock Internal clock (ø/64, ø/16, ø/4, ø) Baud rate generator Clock Transmit/receive SCR3 control Interrupt requests (TEI, TXI, Legend: RXI, ERI) RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR:...
Page 226: Register Descriptions
Pin Configuration: Table 10.4 shows the SCI3 pin configuration. Table 10.4 Pin Configuration Name Abbrev. Function SCI3 clock SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output Register Configuration: Table 10.5 shows the SCI3 internal register configuration. Table 10.5 SCI3 Registers Name Abbrev.
Page 227 Receive Data Register (RDR) RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 Initial value Read/Write The receive data register (RDR) is an 8-bit register for storing received serial data. Each time a byte of data is received, the received data is transferred from the receive shift register (RSR) to RDR, completing a receive operation.
Page 228 Transmit Data Register (TDR) TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Initial value Read/Write The transmit data register (TDR) is an 8-bit register for holding transmit data. When SCI3 detects that the transmit shift register (TSR) is empty, it shifts transmit data written in TDR to TSR and starts serial data transmission.
Page 229 Bit 6: CHR Description 8-bit data (initial value) 7-bit data* Note: * When 7-bit data is selected as the character length in asynchronous mode, the MSB (bit 7) in the transmit data register is not transmitted. Bit 5—Parity Enable (PE): In asynchronous mode, bit 5 selects whether or not a parity bit is to be added to transmitted data and checked in received data.
Page 230 Bit 3—Stop Bit Length (STOP): Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. This setting is valid only in asynchronous mode. In synchronous mode a stop bit is not added, so this bit is ignored. Bit 3: STOP Description 1 stop bit *...
Page 231 Serial Control Register 3 (SCR3) MPIE TEIE CKE1 CKE0 Initial value Read/Write Serial control register 3 (SCR3) is an 8-bit register that controls SCI3 transmit and receive operations, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the serial clock source.
Page 232 Bit 5—Transmit Enable (TE): Bit 5 enables or disables the start of a transmit operation. Bit 5: TE Description Transmit operation disabled * (TXD is the transmit data pin) (initial value) Transmit operation enabled * (TXD is the transmit data pin) Notes: 1.
Page 233 Bit 2—Transmit End Interrupt Enable (TEIE): Bit 2 enables or disables the transmit end interrupt (TEI) requested if there is no valid transmit data in TDR when the MSB is transmitted. Bit 2: TEIE Description Transmit end interrupt (TEI) disabled (initial value) Transmit end interrupt (TEI) enabled* Note: * A TEI interrupt can be cleared by clearing the SSR bit TDRE to 0 and clearing the transmit...
Page 234 Serial Status Register (SSR) TDRE RDRF TEND MPBR MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only a write of 0 for flag clearing is possible. The serial status register (SSR) is an 8-bit register containing status flags for indicating SCI3 states, and containing the multiprocessor bits.
Page 235 Bit 6—Receive Data Register Full (RDRF): Bit 6 is a status flag indicating whether there is receive data in RDR. Bit 6: RDRF Description Indicates there is no receive data in RDR (initial value) [Clearing conditions] • After reading RDRF = 1, cleared by writing 0 to RDRF. •...
Page 236 Bit 4: Framing Error (FER): Bit 4 is a status flag indicating that a framing error has occurred during asynchronous receiving. Bit 4: FER Description Indicates that data receiving is in progress or has been completed * (initial value) [Clearing condition] After reading FER = 1, cleared by writing 0 to FER Indicates that a framing error occurred in data receiving [Setting condition]...
Page 237 Bit 2—Transmit End (TEND): Bit 2 is a status flag indicating that TDRE was set to 1 when the last bit of a transmitted character was sent. TEND is a read-only bit and cannot be modified. Bit 2: TEND Description Indicates that transmission is in progress [Clearing conditions] •...
Page 238 Bit Rate Register (BRR) BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value Read/Write The bit rate register (BRR) is an 8-bit register which, together with the baud rate generator clock selected by bits CKS1 and CKS0 in the serial mode register (SMR), sets the transmit/receive bit rate.
Page 239 Table 10.6 BRR Settings and Bit Rates in Asynchronous Mode OSC (MHz) 2.4576 4.194304 Bit Rate Error Error Error Error (bits/s) +0.03 +0.31 +0.03 –0.04 +0.16 +0.16 +0.21 +0.16 +0.16 +0.21 +0.16 +0.16 +0.21 1200 +0.16 +0.16 –0.70 2400 +0.16 +0.16 +1.14 4800...
Page 240 Table 10.6 BRR Settings and Bit Rates in Asynchronous Mode (cont) OSC (MHz) 9.8304 Bit Rate Error Error (bits/s) +0.31 –0.25 +0.16 +0.16 +0.16 1200 +0.16 2400 +0.16 4800 –1.36 9600 +1.73 19200 +1.73 31250 –1.70 38400 +1.73 Notes: 1. Settings should be made so that error is within 1%. 2.
Page 241 3. The error values in table 10.6 were derived by performing the following calculation and rounding off to two decimal places. B – R × 100 Error (%) = B: Bit rate found from n, N, and OSC R: Bit rate listed in left column of table 10.6 Table 10.8 shows the maximum bit rate for selected frequencies in asynchronous mode.
Page 242 Table 10.9 Typical BRR Settings and Bit Rates (Synchronous Mode) OSC (MHz) Bit Rate (bits/s) — — — — — — — — — — — — — — 2.5K 100K — — — — 250K 500K — — — —...
Page 243: Operation
Table 10.10 Relation between n and Clock SMR Setting Clock CKS1 CKS0 ø ø/4 ø16 ø/64 10.3.3 Operation SCI3 supports serial data communication in both asynchronous mode, where each character transferred is synchronized separately, and synchronous mode, where transfer is synchronized by clock pulses.
Page 244  When an external clock is selected: The internal baud rate generator is not used. Operation is synchronous with the input clock. Table 10.11 SMR Settings and SCI3 Communication Format SMR Setting Communication Format Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: Multipro-...
Page 245 Table 10.12 SMR and SCR3 Settings and Clock Source Selection SCR3 Transmit/Receive Clock Bit 7: Bit 1: Bit 0: Clock CKE1 CKE0 Mode Source Pin SCK Function Asynchronous Internal I/O port (SCK pin not used) mode Outputs clock with same frequency as bit rate External Clock should be input with frequency...
Page 246 Continuous Transmit/Receive Operation Using Interrupts: Continuous transmit and receive operations are possible with SCI3, using the RXI or TXI interrupts. Table 10.13 explains this use of these interrupts. Table 10.13 Transmit/Receive Interrupts Interrupt Flag Interrupt Conditions Remarks RDRF When serial data is received normally The RXI interrupt handling routine and receive data is transferred from reads the receive data from RDR...
Page 247 ↑ RSR (receiving) (received and transferred) ← RDRF = 0 RDRF (RXI requested if RIE = 1) Figure 10.4 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) ↓ (transmission complete, TSR (transmitting) next data transferred) ← TDRE = 0 TDRE (TXI requested if TIE = 1) Figure 10.4 (b) TDRE Setting and TXI Interrupt...
Page 248: Operation In Asynchronous Mode
10.3.4 Operation in Asynchronous Mode In asynchronous communication mode, a start bit indicating the start of communication and a stop bit indicating the end of communication are added to each character that is sent/received. In this way synchronization is achieved for each character as a self-contained unit. SCI3 consists of independent transmit and receive modules, giving it the capability of full duplex communication.
Page 249 Table 10.14 shows the 12 formats that can be selected in asynchronous mode. The format is selected in the serial mode register (SMR). Table 10.14 Serial Communication Formats in Asynchronous Mode SMR Settings Serial Communication Format and Frame Length STOP 8-bit data STOP 8-bit data...
Page 250 (2) Clock: The clock source is determined by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3). See table 10.12 for the settings. Either an internal clock source can be used to run the built-in baud rate generator, or an external clock source can be input at pin When an external clock source is input to pin SCK , it should have a frequency 16 times the desired bit rate.
Page 251 Figure 10.7 shows a typical flow chart for SCI3 initialization. Start Clear TE and RE to 0 in SCR3 Select the clock using serial control register 3(SCR3). Be sure to set 0 for other unused bits. When the clock output is selected in the asynchronous mode, a clock signal is Set bits CKE1 and CKE0 output immediately after setting bits CKE1...
Page 252 Transmitting: Figure 10.8 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below. Start Read bit TDRE in SSR Read the serial status register (SRR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR).
Page 253 SCI3 operates as follows during data transmission in asynchronous mode. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts.
Page 254 Start 1. Read bits OER, PER, and FER in the serial status Read bits OER, PER, and register (SSR) to FER in SSR determine if a receive error has occurred. OER + PER + If a receive error has FER = 1 occurred, receive error processing is executed.
Page 255 SCI3 operates as follows when receiving serial data in asynchronous mode. SCI3 monitors the communication line, and when a start bit (0) is detected it performs internal synchronization and starts receiving. The communication format for data receiving is as outlined in table 10.14.
Page 256: Operation In Synchronous Mode
Figure 10.11 shows a typical SCI3 data receive operation in asynchronous mode. Start Receive Parity Stop Start Receive Parity Stop Mark data data (idle state) Serial data 1 frame 1 frame RDRF SCI3 operation RXI request RDRF cleared Detects stop bit = 0 to 0 ERI request due to framing error...
Page 257 (1) Transmit/Receive Format: Figure 10.12 shows the general communication data format for synchronous communication. Serial clock Don't Don't Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 care care 8 bits One unit of communication data (character or frame) Note: At high level except during continuous transmit/receive.
Page 258 Note: When modifying the operation mode, transfer format or other settings, always be sure to clear bits TE and RE first. When TE is cleared to 0, bit TDRE will be set to 1. Clearing RE does not clear the status flags RDRF, PER, FER, or OER, or alter the contents of the receive data register (RDR).
Page 259 Transmitting: Figure 10.14 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below. Start Read bit TDRE in SSR Read the serial status register (SSR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR).
Page 260 SCI3 operates as follows during data transmission in synchronous mode. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts.
Page 261 Receiving: Figure 10.16 shows a typical flow chart for receiving data. After SCI3 initialization, follow the procedure below. Start 1. Read bit OER in the serial status register (SSR) Read bit OER in SSR to determine if an error has occurred. If an overrun error has occurred, overrun error processing is executed.
Page 262 SCI3 operates as follows when receiving serial data in synchronous mode. In synchronization with the input or output of the serial clock, SCI3 initializes internally and starts receiving. Received data is set in RSR from LSB to MSB. After data has been received, SCI3 checks to confirm that the value of bit RDRF is 0 indicating that received data can be transferred from RSR to RDR.
Page 263 Simultaneous Transmit/Receive: Figure 10.18 shows a typical flow chart for transmitting and receiving simultaneously. After SCI3 synchronization, follow the procedure below. Read the serial status register (SSR), Start and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR).
Page 264: Multiprocessor Communication Function
Notes: 1. To switch from transmitting to simultaneous transmitting and receiving, first confirm that TDRE and TEND are both set to 1 and that SCI3 has finished transmitting. Next clear TE to 0. Then set both TE and RE to 1. 2.
Page 265 Transmitting processor Communication line Receiving Receiving Receiving Receiving processor A processor B processor C processor D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID-sending cycle Data-sending cycle (receiving processor (data sent to receiving...
Page 266 Transmitting Multiprocessor Data: Figure 10.20 shows a typical flow chart for multiprocessor serial data transmission. After SCI3 initialization, follow the procedure below. Start Read bit TDRE in SSR Read the serial status register (SSR), and after confirming that bit TDRE = 1, set bit MPBT (multiprocessor bit transmit) in SSR to 0 or 1, then write transmit data in the TDRE = 1?
Page 267 SCI3 operates as follows during data transmission using a multiprocessor format. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts.
Page 268 Receiving Multiprocessor Ddata: Figure 10.22 shows a typical flow chart for receiving data using a multiprocessor format. After SCI3 initialization, follow the procedure below. Start Set bit MPIE in SCR3 to 1 Set bit MPIE in serial control register 3 (SCR3) to 1. Read bits OER and FER in SSR Read bits OER and FER in the serial status register (SSR) to determine if an error has occurred.
Page 269 Figure 10.23 gives an example of data reception using a multiprocessor format. Start Receive Stop Start Receive Stop Mark data (ID1) data (data 1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value SCI3 operation RXI request RDRF cleared to 0 No RXI request MPIE cleared to 0 RDR state retained...
Page 270: Interrupts
10.3.7 Interrupts SCI3 has six interrupt sources: transmit end, transmit data empty, receive data full, and the three receive error interrupts (overrun error, framing error, and parity error). All share a common interrupt vector. Table 10.16 describes each interrupt. Table 10.16 SCI3 Interrupts Interrupt Interrupt Request Vector Address...
Page 271: Application Notes
10.3.8 Application Notes When using SCI3, attention should be paid to the following matters. Relation between Bit TDRE and Writing Data to TDR: Bit TDRE in the serial status register (SSR) is a status flag indicating that TDR does not contain new transmit data. TDRE is automatically cleared to 0 when data is written to TDR.
Page 272 Break Detection and Processing: Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state SCI3 continues to receive, so if the FER bit is cleared to 0 it will be set to 1 again.
Page 273 16 clock cycles 8 clock cycles 15 0 Internal base clock Receive data Start bit (RXD) Synchronization sampling timing Data sampling timing Figure 10.24 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be derived from the following equation. ...
Page 274 Relationship between Bit RDRF and Reading RDR: While SCI3 is receiving, it checks the RDRF flag. If the RDRF flag is cleared to 0 when the reception of one frame of data is completed, data reception ends normally. If RDRF is set to 1, an overrun error occurs. RDRF is automatically cleared to 0 when the contents of RDR are read.
Page 275: Section 11 Dtmf Generator
Section 11 DTMF Generator 11.1 Overview The H8/3637 Series has an on-chip dual-tone multifrequency (DTMF) generator that can generate DTMF signals. A DTMF signal accesses a telephone switching system by a pair of sine waves. Figure 11.1 shows the frequency matrix. The DTMF generator generates frequencies corresponding to the numbers and symbols on the keypad of a telephone set or facsimile machine.
Page 276: Block Diagram
Sine waves are output from a high-precision resistor-ladder-type D/A converter. Each cycle is divided into 32 segments to give a stable waveform with low distortion. • Composite or single waveform output Register settings can select combined row-and-column-group output, or independent row- group or column-group output.
Page 277: Pin Configuration
11.1.3 Pin Configuration Table 11.1 shows the pins assigned to the DTMF generator. Table 11.1 Pin Configuration Name Abbrev. Function DTMF output reference level — Reference level voltage for DTMF power supply pin output DTMF signal output pin TONED Output DTMF signal output 11.1.4 Register Configuration...
Page 278 11.2 Register Descriptions 11.2.1 DTMF Control Register (DTCR) DTEN — CLOE RWOE CLF1 CLF0 RWF1 RWF0 Initial value Read/Write — DTCR is an 8-bit read/write register that enables the DTMF generator, enables row and column output, and selects the output frequencies. Upon reset, DTCR is initialized to H'40.
Page 279 Bits 3 and 2—DTMF Column Signal Output Frequency 1 and 0 (CLF1, CLF0): Bits 3 and 2 select the DTMF column signal frequency (C1 to C4). Bit 3: CLF1 Bit 2: CLF0 Description DTMF column signal output frequency: 1209 Hz (C1) (initial value) DTMF column signal output frequency: 1336 Hz (C2) DTMF column signal output frequency: 1447 Hz (C3)
Page 280 11.2.2 DTMF Load Register (DTLR) — — — DTL4 DTL3 DTL2 DTL1 DTL0 Initial value Read/Write — — — DTLR is an 8-bit read/write register that specifies the ratio by which the clock frequency at the OSC pins is divided for input to the DTMF generator. Upon reset, DTLR is initialized to H'E0.
Page 281: Operation
11.3 Operation 11.3.1 Output Waveform The DTMF generator outputs a row-group or column-group sine wave (DTMF signal) or a combined row-column waveform at the TONED pin. These signals are generated by a high- precision resistor-ladder-type D/A converter circuit. The output frequency is selected by DTCR. Figure 11.3 shows an equivalent circuit for the TONED output.
Page 282 Table 11.3 indicates the frequency deviation between the DTMF signals output by the DTMF generator and the nominal (standard) signal values. Table 11.3 Frequency Deviation of DTMF Signals from Nominal Signals Standard Signal DTMF Signal Frequency Symbol Frequency (Hz) Output (Hz) Deviation (%) 694.44 –0.37...
Page 283: Typical Use
Figure 11.5 shows an example of the use of the DTMF generator. 24 kΩ TONED DTMF 2 kΩ HA16808ANT ref1 H8/3637 +0.47 µF 100 kΩ MUTE 360 k Ω 2SC458 Note: Numbers at ends of signal lines are pin numbers of HA16808ANT.
Page 284: Section 12 A/D Converter
Section 12 A/D Converter 12.1 Overview The H8/3637 Series includes on-chip a resistance-ladder-based successive-approximation analog- to-digital converter, and can convert up to four channels of analog input. 12.1.1 Features The A/D converter has the following features. • 8-bit resolution • 4 input channels •...
Page 285: Block Diagram
12.1.2 Block Diagram Figure 12.1 shows a block diagram of the A/D converter. ADTRG Multiplexer ADSR Com- Control logic parator – Reference voltage ADRR Legend: AMR: A/D mode register IRRAD ADSR: A/D start register ADRR: A/D result register IRRAD: A/D converter interrupt request flag Figure 12.1 Block Diagram of the A/D Converter...
Page 286: Pin Configuration
12.1.3 Pin Configuration Table 12.1 shows the A/D converter pin configuration. Table 12.1 Pin Configuration Name Abbrev. Function Analog power supply pin Input Power supply of analog part Analog ground pin Input Ground and reference voltage of analog part Analog input pin 4 Input Analog input channel 4 Analog input pin 5...
Page 287: Register Descriptions
12.2 Register Descriptions 12.2.1 A/D Result Register (ADRR) ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-to- digital conversion.
Page 288 Bit 7—Clock Select (CKS): Bits CKS and CKS1 select the A/D conversion speed. Conversion Time Bit 5: CKS1 Bit 7: CKS Conversion Period ø = 2 MHz ø = 5 MHz Reserved (initial value) — — 62 µs 24.8 µs 124/ø...
Page 289: A/D Start Register (Adsr)
12.2.3 A/D Start Register (ADSR) ADSF — — — — — — — Initial value Read/Write — — — — — — — The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D conversion. A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated edge of the external trigger signal, which also sets ADSF to 1.
Page 290: Operation
12.3 Operation 12.3.1 A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 8-bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1.
Page 291: Typical Use
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 2 (IENR2). For further details see 3.3, Interrupts. 12.5 Typical Use An example of how the A/D converter can be used is given below, using channel 4 (pin AN ) as the analog input channel.
Page 292 Figure 12.3 Typical A/D Converter Operation Timing...
Page 293 Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR ADSF = 0? Read ADRR data Perform A/D conversion? Figure 12.4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software)
Page 294: Application Notes
Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? Clear bit IRRAD to 0 in IRR2 Read ADRR data Perform A/D conversion? Figure 12.5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used) 12.6 Application Notes •...
Page 295: Section 13 14-Bit Pulse Width Modulator (Pwm)
Section 13 14-bit Pulse Width Modulator (PWM) 13.1 Overview The H8/3637 Series is provided with a 14-bit pulse width modulator (PWM). The PWM can be used as a D/A converter by connecting a low-pass filter. 13.1.1 Features Features of the 14-bit PWM are given below.
Page 296: Pin Configuration
13.1.3 Pin Configuration Table 13.1 shows the 14-bit PWM output pin. Table 13.1 Pin Configuration Name Abbrev. Function PWM output Output Pulse-division PWM waveform output pin 13.1.4 Register Configuration Table 13.2 shows the 14-bit PWM register configuration. Table 13.2 14-Bit PWM Register Name Abbrev.
Page 297: Pwm Data Registers U And L (Pwdru, Pwdrl)
Bit 0—Clock Select 0 (PWCR0): Bit 0 selects the clock supplied to the 14-bit PWM. It is a write-only bit, and is always read as 1. Bit 0: PWCR0 Description Input clock ø/2 (tø* = 2/ø) (initial value) PWM waveform generated with conversion cycle of 16,384/ø and minimum transition width of 1/ø...
Page 298: Operation
13.3 Operation When using the 14-bit PWM, register settings should be carried out in the following order: 1. Set PWM in PMR1 to 1 to designate the P1 /PWM pin as the PWM output pin. 2. Use PWCR0 in PWCR to select either 32,768/ø (PWCR0 = 1) or 16,384/ø (PWCR0 = 0) as the conversion period.
Page 299: Section 14 Electrical Characteristics
Section 14 Electrical Characteristics 14.1 Absolute Maximum Ratings Table 14.1 lists the absolute maximum ratings. Table 14.1 Absolute Maximum Ratings Item Symbol Value Unit Notes Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0 Reference level supply voltage –0.3 to V +0.3 Programming voltage...
Page 300: Electrical Characteristics
14.2 Electrical Characteristics 14.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures below. Note: Caution is required during development, since the guaranteed operating ranges of the chip and development tools are different.
Page 301 Power Supply Voltage vs. Clock Frequency Range 16.384 8.192 4.096 • Active mode (high speed) • Subactive mode • Sleep mode (except CPU) • Subsleep mode (except CPU) • Watch mode (except CPU) 625.0 500.0 312.5 62.5 • Active mode (medium speed) Analog Power Supply Voltage vs.
Page 302: Dc Characteristics
14.2.2 DC Characteristics Table 14.2 lists the DC characteristics. Table 14.2 DC Characteristics = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20 to +75°C, including subactive mode, unless otherwise indicated. Item Symbol Applicable Pins...
Page 303 Table 14.2 DC Characteristics (cont) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20 to +75°C, including subactive mode, unless otherwise indicated. Item Symbol Applicable Pins Unit Test Condition Note Input low...
Page 304 Table 14.2 DC Characteristics (cont) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20 to +75°C, including subactive mode, unless otherwise indicated. Item Symbol Applicable Pins Unit Test Condition Note µ...
Page 305 Table 14.2 DC Characteristics (cont) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20 to +75°C, including subactive mode, unless otherwise indicated. Applicable Item Symbol Pins Unit Test Condition Notes Active mode current...
Page 306 Table 14.2 DC Characteristics (cont) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20 to +75°C, including subactive mode, unless otherwise indicated. Item Symbol Applicable Pins Unit Test Condition Allowable output low Output pins except in...
Page 307: Ac Characteristics
14.2.3 AC Characteristics Table 14.3 lists the control signal timing, and tables 14.4 and 14.5 list the serial interface timing. Table 14.3 Control Signal Timing = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20 to +75°C, including subactive mode, unless otherwise specified.
Page 308 Table 14.3 Control Signal Timing (cont) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20 to +75°C, including subactive mode, unless otherwise specified. Applicable Reference Item Symbol Pins Min Typ Unit...
Page 309 Table 14.4 Serial Interface Timing (SCI1) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20 to +75°C, including subactive mode, unless otherwise specified. Applicable Reference Item Symbol Pins Unit Test Condition...
Page 310: A/D Converter Characteristics
14.2.4 A/D Converter Characteristics Table 14.6 shows the A/D converter characteristics. Table 14.6 A/D Converter Characteristics = 2.7 V to 5.5 V, AV = 0.0 V, T = –20 to +75°C, unless otherwise specified. Item Symbol Applicable Pins Unit Test Condition Notes Analog power —...
Page 311: Dtmf Characteristics
14.2.5 DTMF Characteristics Table 14.7 lists the DTMF generator characteristics. Table 14.7 DTMF Characteristics = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20 to +75˚C, unless otherwise specified Applicable Item Symbol...
Page 312: Operation Timing
14.3 Operation Timing Figures 14.1 to 14.6 show operation timings. OSC1 Figure 14.1 System Clock Input Timing Figure 14.2 RES Low Width Timing IRQ to IRQ WKP to WKP ADTRG TMIF, TMIG TMCIY Figure 14.3 Input Timing...
Page 313 Scyc or V or V SCKL SCKH SCKf SCKr Notes: * Output timing reference levels Output high: = 2.0 V Output low: = 0.8 V Refer to figure 14.7 for output load condition. Figure 14.4 Serial Interface 1 Input/Output Timing...
Page 314 SCKW Scyc Figure 14.5 SCK Input Clock Timing Scyc or V or V (transmit data) (receive data) Notes: * Output timing reference levels Output high: = 2.0 V Output low: = 0.8 V Refer to figure 14.7 for output load condition. Figure 14.6 Input/Output Timing of Serial Interface 3 in Synchronous Mode...
Page 315: Output Load Circuits
14.4 Output Load Circuits Figure 14.7 shows an output load condition. 2.4 kΩ Output pin 12 k Ω 30 pF Figure 14.7 Output Load Condition = 100 kΩ TONED Figure 14.8 TONED Load Circuit...
Page 316: Appendix A Cpu Instruction Set
Appendix A CPU Instruction Set Instructions Operation Notation Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter...
Page 317 Table A.1 lists the H8/300L CPU instruction set. Table A.1 Instruction Set Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C #xx:8 → Rd8 MOV.B #xx:8, Rd — — — Rs8 → Rd8 MOV.B Rs, Rd —...
Page 318 Table A.1 Instruction Set (cont) Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C SP–2 → SP PUSH Rs — — 0 — 6 Rs16 → @SP Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — Rd8+Rs8 →...
Page 319 Table A.1 Instruction Set (cont) Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C Rd16÷Rs8 → Rd16 (RdH: DIVXU.B Rs, Rd — — (5) (6) — — remainder, RdL: quotient) Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd —...
Page 320 Table A.1 Instruction Set (cont) Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — (#xx:3 of @Rd16) ← 1 BSET #xx:3, @Rd —...
Page 321 Table A.1 Instruction Set (cont) Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C (#xx:3 of Rd8) → C BLD #xx:3, Rd — — — — — (#xx:3 of @Rd16) → C BLD #xx:3, @Rd —...
Page 322 Table A.1 Instruction Set (cont) Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation Branching Condition I H N Z V C C⊕(#xx:3 of @Rd16) → C BIXOR #xx:3, @Rd — — — — — C⊕(#xx:3 of @aa:8) → C BIXOR #xx:3, @aa:8 —...
Page 323: Operation Code Map
Table A.1 Instruction Set (cont) Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C SP–2 → SP JSR @@aa:8 — — — — — — 8 PC → @SP PC ← @aa:8 PC ← @SP —...
Page 324 Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Page 325 High SLEEP XORC ANDC ADDS ADDX SHLL SHLR ROTXL ROTXR SUBS SUBX SHAL SHAR ROTL ROTR MULXU DIVXU BIST BSET BNOT BCLR BTST BXOR BAND EEPMOV Bit-manipulation instructions BIOR BIXOR BIAND BILD ADDX SUBX Note: The PUSH and POP instructions are identical in machine language to MOV instructions.
Page 326: Number Of Execution States
Number of Execution States The following describes the operation status in each instruction provided for the H8/300 L CPU, as well as a calculation of the number of execution states. Table A.4 gives the number of cycles (as the operation status) for such operations as an instruction fetch, data read/write performed during an instruction execution.
Page 327 Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch — Branch address read Stack operation Byte data access 2 or 3* Word data access — Internal operation Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for details.
Page 328 Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd...
Page 329 Table A.4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 2 BILD BILD #xx:3, Rd...
Page 330 Table A.4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BSET BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 2 BTST BTST #xx:3, Rd BTST #xx:3, @Rd 2...
Page 331 Table A.4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd...
Page 332 Table A.4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ROTXL ROTXL.B Rd ROTXR ROTXR.B Rd SHAL SHAL.B Rd SHAR SHAR.B Rd SHLL SHLL.B Rd SHLR SHLR.B Rd SLEEP...
Page 333: Appendix B On-Chip Registers
Appendix B On-Chip Registers I/O Registers (1) Bit Names Address Register Module (Low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'90 H'91 H'92 H'93 H'94 H'95 H'96 H'97 H'98 PMR1 IRQ3 IRQ2...
Page 334 Bit Names Address Register Module (Low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'AB TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SCI3 H'AC TDRE RDRF TEND MPBR MPBT H'AD RDR7 RDR6...
Page 335 Bit Names Address Register Module (Low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'CD TMY7 — — — — TMY2 TMY1 TMY0 Timer Y H'CE TCYH/ TCYH7/ TCYH6/ TCYH5/ TCYH4/ TCYH3/ TCYH2/...
Page 336 Bit Names Address Register Module (Low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'EE H'EF H'F0 SYSCR1 SSBY STS2 STS1 STS0 LSON — — — System control H'F1 SYSCR2 — —...
Page 337: I/O Registers (2)
I/O Registers (2) Register Register Address to which the Name of acronym name register is mapped on-chip supporting module MTCR—Multitone control register H'90 Multitone generator numbers Initial bit DA0E MTEN — values Initial value Names of the bits. Dashes Read/Write —...
Page 338 PMR1—Port mode register 1 H'98 I/O ports IRQ3 IRQ2 IRQ1 TMIG TMOFH TMOFL TMOW Initial value Read/Write P1 /TMOW pin function switch 0 Functions as P1 I/O pin 1 Functions as TMOW output pin P1 /TMOFL pin function switch 0 Functions as P1 I/O pin 1 Functions as TMOFL output pin P1 /TMOFH pin function switch 0 Functions as P1 I/O pin...
Page 339 PMR2—Port mode register 2 H'99 I/O ports IRQ0 — POF1 SCK1 IRQ4 Initial value Read/Write — P2 /IRQ /ADTRG pin function switch 0 Functions as P2 I/O pin 1 Functions as IRQ /ADTRG input pin P2 /SCK pin function switch 0 Functions as P2 I/O pin 1 Functions as SCK I/O pin P2 /SI pin function switch...
Page 340 PMR6—Port mode register 6 H'9A I/O ports — — — — — — — Initial value Read/Write — — — — /TXD pin function switch 0 Functions as P2 I/O pin 1 Functions as TXD output pin PMR5—Port mode register 5 H'9B I/O ports Initial value...
Page 341 PUCR5—Port pull-up control register 5 H'9E I/O ports PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 Initial value Read/Write PUCR6—Port pull-up control register 6 H'9F I/O ports PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 Initial value Read/Write...
Page 342 SCR1—Serial control register 1 H'A0 SCI1 SNC1 SNC0 — — CKS3 CKS2 CKS1 CKS0 Initial value Read/Write Clock select Transfer Clock Cycle Bit 2 Bit 1 Bit 0 Synchronous Prescaler CKS2 CKS1 CKS0 Division ø = 5 MHz ø = 2.5 MHz 204.8 µs 409.6 µs ø/1024...
Page 343 SCSR1—Serial control/status register 1 H'A1 SCI1 — ORER — — — — Initial value Read/Write — R/(W) — — — Start flag Read Indicates that transfer is stopped Write Invalid Read Indicates transfer in progress Write Starts a transfer operation Overrun error flag 0 [Clearing condition] After reading 1, cleared by writing 0...
Page 344 SDRL—Serial data register L H'A3 SCI1 SDRL7 SDRL6 SDRL5 SDRL4 SDRL3 SDRL2 SDRL1 SDRL0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Stores transmit and receive data 8-bit transfer mode: 8-bit data 16-bit transfer mode: Lower 8 bits of data PWCR—PWM control register H'A4 14-bit PWM...
Page 345 PWDRL—PWM data register L H'A6 14-bit PWM PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Initial value Read/Write Lower 8 bits of PWM waveform generation data SMR—Serial mode register H'A8 SCI3 STOP CKS1 CKS0 Initial value Read/Write Clock select 0, 1 ø...
Page 346 BRR—Bit rate register H'A9 SCI3 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value Read/Write...
Page 347 SCR3—Serial control register 3 H'AA SCI3 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable Bit 1 Bit 0 Description CKE1 CKE0 Communication Mode Clock Source SCK Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock Serial clock output Asynchronous Internal clock Clock output...
Page 348 TDR—Transmit data register H'AB SCI3 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Initial value Read/Write Data to be transferred to TSR...
Page 349 SSR—Serial status register H'AC SCI3 TDRE RDRF TEND MPBR MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit receive Multiprocessor bit transmit 0 Indicates reception of data in which the multiprocessor bit is 0 0 The multiprocessor bit in transmit data is 0 1 Indicates reception of data in which the multiprocessor bit is 1 1 The multiprocessor bit in transmit data is 1 Transmit end...
Page 350 RDR—Receive data register H'AD SCI3 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 Initial value Read/Write TMA—Timer mode register A H'B0 Timer A TMA7 TMA6 TMA5 — TMA3 TMA2 TMA1 TMA0 Initial value Read/Write — Clock output select Internal clock select ø/32 Prescaler and Divider Ratio TMA3 TMA2...
Page 351 TCA—Timer counter A H'B1 Timer A TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA0 TCA1 Initial value Read/Write Count value...
Page 352 DTCR—DTMF control register H'B2 DTMF generator DTEN — CLOE RWOE CLF1 CLF0 RWF1 RWF0 Initial value Read/Write — DTMF row signal output frequency 1 and 0 RWF1 RWF0 DTMF row signal output frequency 697 Hz (R1) 770 Hz (R2) 852 Hz (R3) 941 Hz (R4) DTMF column signal output frequency 1 and 0 CLF1...
Page 353 DTLR—DTMF load register H'B3 DTMF generator — — — DTL4 DTL3 DTL2 DTL0 DTL1 Initial value Read/Write — — — OSC clock division ratio 4 to 0 DTL4 DTL3 DTL2 DTL1 DTL0 Division Ratio OSC Clock Frequency Illegal setting (initial value) Illegal setting Illegal setting 1.2 MHz...
Page 354 TCSRW—Timer control/status register W H'B4 Watchdog timer B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* Watchdog timer reset 0 [Clearing conditions] • Reset by RES pin • When 0 is written to WRST while writing 0 to B0WI when TCSRWE is set to 1 1 [Setting condition]...
Page 355 TCW—Timer counter W H'B5 Watchdog timer TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value Read/Write Count value TCRF—Timer control register F H'B6 Timer F TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value Read/Write Toggle output level H Clock select L 0 Low level External event (TMIF): Rising or falling edge...
Page 356 TCSRF—Timer control/status register F H'B7 Timer F OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value Read/Write R/(W) R/(W) R/(W) R/(W) Timer overflow interrupt enable L 0 TCFL overflow interrupt disabled 1 TCFL overflow interrupt enabled Compare match flag L 0 [Clearing condition] After reading CMFL = 1, cleared by writing 0 to CMFL 1 [Setting condition]...
Page 357 TCFH—8-bit timer counter FH H'B8 Timer F TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH0 TCFH1 Initial value Read/Write Count value TCFL—8-bit timer counter FL H'B9 Timer F TCFL7 TCFL6 TCFL5 TCFL4 TCFL3 TCFL2 TCFL1 TCFL0 Initial value Read/Write Count value OCRFH—Output compare register FH H'BA Timer F...
Page 358 TMG—Timer mode register G H'BC Timer G OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value Read/Write R/(W) R/(W) Clock select Internal clock: ø/64 Internal clock: ø/32 Internal clock: ø/2 Internal clock: ø /2 Counter clear TCG is not cleared TCG is cleared at the falling edge of the input capture signal TCG is cleared at the rising edge of the input capture signal TCG is cleared at both edges of the input capture signal...
Page 359 ICRGF—Input capture register GF H'BD Timer G ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF0 ICRGF1 Initial value Read/Write ICRGR—Input capture register GR H'BE Timer G ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 Initial value Read/Write...
Page 360 AMR—A/D mode register H'C4 A/D converter TRGE CKS1 — Initial value Read/Write — Channel select Bit 3 Bit 2 Bit 1 Bit 0 Analog input channel No channel selected Reserved Reserved Don’t care External trigger select 0 Disables start of A/D conversion by external trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG Clock select...
Page 361 ADSR—A/D start register H'C6 A/D converter ADSF — — — — — — — Initial value Read/Write — — — — — — — A/D start flag 0 [Read] Indicates the completion of A/D conversion [Write] Stops A/D conversion [Read] Indicates A/D conversion in progress [Write] Starts A/D conversion...
Page 362 TCYH—Timer counter YH H'CE Timer Y TCYH7 TCYH6 TCYH5 TCYH4 TCYH3 TCYH2 TCYH1 TCYH0 Initial value Read/Write Count value TLYH—Timer load register YH H'CE Timer Y TLYH7 TLYH6 TLYH5 TLYH4 TLYH3 TLYH2 TLYH1 TLYH0 Initial value Read/Write Reload value setting TCYL—Timer counter YL H'CF Timer Y...
Page 363 PDRE—Port data register E H'D3 I/O ports — — — — — — Initial value Read/Write — — — — — — PDR1—Port data register 1 H'D4 I/O ports Initial value Read/Write PDR2—Port data register 2 H'D5 I/O ports Initial value Read/Write PDR5—Port data register 5 H'D8...
Page 364 PDR7—Port data register 7 H'DA I/O ports Initial value Read/Write PDR8—Port data register 8 H'DB I/O ports Initial value Read/Write PDR9—Port data register 9 H'DC I/O ports Initial value Read/Write PDRA—Port data register A H'DD I/O ports — — — —...
Page 365 PCRE—Port control register E H'E3 I/O ports — — — — PCRE PCRE — — Initial value Read/Write — — — — — — Port E input/output select 0 Input pin 1 Output pin PCR1—Port control register 1 H'E4 I/O ports PCR1 PCR1 PCR1...
Page 366 PCR5—Port control register 5 H'E8 I/O ports PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 Initial value Read/Write Port 5 input/output select 0 Input pin 1 Output pin PCR6—Port control register 6 H'E9 I/O ports PCR6 PCR6 PCR6 PCR6 PCR6 PCR6 PCR6 PCR6...
Page 367 PCR8—Port control register 8 H'EB I/O ports PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 Initial value Read/Write Port 8 input/output select 0 Input pin 1 Output pin PCR9—Port control register 9 H'EC I/O ports PCR9 PCR9 PCR9 PCR9 PCR9 PCR9 PCR9 PCR9...
Page 368 SYSCR1—System control register 1 H'F0 System control SSBY STS2 STS1 STS0 LSON — — — Initial value Read/Write — — — Low speed on flag 0 The CPU operates on the system clock (ø) 1 The CPU operates on the subclock (ø Standby timer select 2 to 0 Wait time = 8,192 states Wait time = 16,384 states...
Page 369 SYSCR2—System control register 2 H'F1 System control — — — NESEL DTON MSON Initial value Read/Write — — — Medium speed on flag Subactive mode clock select 0 Operates in active (high-speed) mode ø /8 1 Operates in active (medium-speed) mode ø...
Page 370 IEGR—IRQ edge select register H'F2 System control — — — IEG4 IEG3 IEG2 IEG1 IEG0 Initial value Read/Write — — — IRQ edge select 0 Falling edge of IRQ pin input is detected 1 Rising edge of IRQ pin input is detected IRQ edge select 0 Falling edge of IRQ pin input is detected 1 Rising edge of IRQ pin input is detected...
Page 371 IENR1—Interrupt enable register 1 H'F3 System control IENTA IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0 Initial value Read/Write IRQ to IRQ interrupt enable 0 Disables interrupt requests from IRQ to IRQ Enables interrupt requests from IRQ to IRQ Wakeup interrupt enable 0 Disables interrupt requests from WKP to WKP Enables interrupt requests from WKP to WKP SCI1 interrupt enable...
Page 372 IENR2—Interrupt enable register 2 H'F4 System control IENDT IENAD — IENTG IENTFH IENTFL IENTY — Initial value Read/Write — — Timer Y interrupt enable Disables timer Y interrupts Enables timer Y interrupts Timer FL interrupt enable 0 Disables timer FL interrupts 1 Enables timer FL interrupts Timer FH interrupt enable 0 Disables timer FH interrupts...
Page 373 IRR1—Interrupt request register 1 H'F6 System control IRRTA IRRS1 — IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 Initial value Read/Write — IRQ to IRQ interrupt request flag 0 [Clearing condition] When IRRIn = 1, it is cleared by writing 0 to IRRIn. 1 [Setting condition] When pin IRQ is set to interrupt input and the designated signal edge is detected.
Page 374 IRR2—Interrupt request register 2 H'F7 System control IRRDT IRRAD — IRRTG IRRTFH IRRTFL IRRTY IRRTYC Initial value Read/Write — Timer Y interrupt request clear flag This is a special bit for clearing the IRRTY interrupt request flag. Writing 0 to this bit clears bit 1 (IRRTY) to 0. Note that writing 0 to this bit does not give the bit itself a value of 0.
Page 375 IWPR—Wakeup interrupt request register H'F9 System control IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value Read/Write Wakeup interrupt request flag 0 [Clearing condition] When IWPFn = 1, it is cleared by writing 0. 1 [Setting condition] When pin WKP is set to interrupt input and a falling signal edge is detected.
Page 376: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams Port 1 Block Diagrams SBY (low level during reset and in standby mode) Internal data bus PUCR1 PMR1 PDR1 PCR1 Timer F module TMIF PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1:...
Page 377 SBY (low level during reset and in standby mode) Internal data bus PUCR1 PMR1 PDR1 PCR1 Timer Y module TMCIY PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1 (b) Port 1 Block Diagram (Pin P1...
Page 378 SBY (low level during reset and in standby mode) Internal data bus PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1 (c) Port 1 Block Diagram (Pin P1...
Page 379 PWM module Internal data bus PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1 (d) Port 1 Block Diagram (Pin P1...
Page 380 Internal data bus PUCR1 PMR1 PDR1 PCR1 Timer G module TMIG PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1 (e) Port 1 Block Diagram (Pin P1...
Page 381 Timer F module TMOFH (P1 TMOFL (P1 Internal data bus PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 n = 2, 1 Figure C.1 (f) Port 1 Block Diagram (Pins P1 and P1...
Page 382 Timer A module TMOW Internal data bus PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1 (g) Port 1 Block Diagram (Pin P1...
Page 383: Port 2 Block Diagrams
Port 2 Block Diagrams Internal data bus PUCR2 PMR2 PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PUCR2: Port pull-up control register 2 Figure C.2 (a) Port 2 Block Diagram (Pin P2...
Page 384 SCI3 module PMR6 PUCR2 PDR2 Internal data bus PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PMR6: Port mode register 6 PUCR2: Port pull-up control register 2 Figure C.2 (b) Port 2 Block Diagram (Pin P2...
Page 385 SCI3 module PUCR2 PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PUCR2: Port pull-up control register 2 Figure C.2 (c) Port 2 Block Diagram (Pin P2...
Page 386 SCI3 module SCKIE SCKOE SCKO SCKI PUCR2 PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PUCR2: Port pull-up control register 2 Figure C.2 (d) Port 2 Block Diagram (Pin P2...
Page 387 SCI1 module PMR2 Internal data bus PUCR2 PMR2 PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PUCR2: Port pull-up control register 2 Figure C.2 (e) Port 2 Block Diagram (Pin P2...
Page 388 Internal data bus PUCR2 PMR2 PDR2 PCR2 SCI module PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PUCR2: Port pull-up control register 2 Figure C.2 (f) Port 2 Block Diagram (Pin P2...
Page 389 SCI module EXCK SCKO SCKI PUCR2 PMR2 PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PUCR2: Port pull-up control register 2 Figure C.2 (g) Port 2 Block Diagram (Pin P2...
Page 390 Internal data bus PUCR2 PMR2 PDR2 PCR2 A/D module ADTRG PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PUCR2: Port pull-up control register 2 Figure C.2 (h) Port 2 Block Diagram (Pin P2...
Page 391: Port 5 Block Diagram
Port 5 Block Diagram Internal data bus PUCR5 PMR5 PDR5 PCR5 PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 PUCR5: Port pull-up control register 5 n = 0 to 7 Figure C.3 Port 5 Block Diagram...
Page 392: Port 6 Block Diagram
Port 6 Block Diagram Internal data bus PUCR6 PDR6 PCR6 PDR6: Port data register 6 PCR6: Port control register 6 PUCR6: Port pull-up control register 6 n = 0 to 7 Figure C.4 Port 6 Block Diagram...
Page 393: Port 7 Block Diagram
Port 7 Block Diagram Internal data bus PDR7 PCR7 PDR7: Port data register 7 PCR7: Port control register 7 n = 0 to 7 Figure C.5 Port 7 Block Diagram...
Page 394: Port 8 Block Diagram
Port 8 Block Diagram Internal data bus PDR8 PCR8 PDR8: Port data register 8 PCR8: Port control register 8 n = 0 to 7 Figure C.6 Port 8 Block Diagram...
Page 395: Port 9 Block Diagram
Port 9 Block Diagram Internal data bus PDR9 PCR9 PDR9: Port data register 9 PCR9: Port control register 9 n = 0 to 7 Figure C.7 Port 9 Block Diagram...
Page 396: Port A Block Diagram
Port A Block Diagram Internal data bus PDRA PCRA PDRA: Port data register A PCRA: Port control register A n = 0 to 3 Figure C.8 Port A Block Diagram Port B Block Diagram Internal data bus A/D module AMR0 to AMR3 n = 4 to 7 Figure C.9 Port B Block Diagram...
Page 397: Port E Block Diagram
C.10 Port E Block Diagram Internal data bus PDRE PCRE PDRE: Port data register E PCRE: Port control register E n = 3, 2 Figure C.10 Port E Block Diagram...
Page 398 Appendix D Port States in the Different Processing States Table D.1 Port States Overview Port Reset Sleep Subsleep Standby Watch Subactive Active to P1 High Retained Retained High Retained Functional Functional impedance impedance* to P2 High Retained Retained High Retained Functional Functional impedance impedance*...
Page 399 Appendix E Product Line-Up Package Product Type Product Code Mark Code (Hitachi Package Code) H8/3637 ZTAT Standard HD6473637F HD6473637F 80-pin QFP (FP-80B) version products HD6473637X HD6473637X 80-pin TQFP (TFP-80F) HD6473637W HD6473637W 80-pin TQFP (TFP-80C) Mask ROM Standard HD6433637F HD6433637(***)F 80-pin QFP (FP-80B)
Page 400 Appendix F Package Dimensions Dimensional drawings of the H8/3637 Series in FP-80B, TFP-80F and TFP-80C packages are shown in figure F.1, F.2 and F.3, respectively. Unit: mm 24.8 ± 0.4 *0.37 ± 0.08 0.15 M 0.35 ± 0.06 0° – 10°...
Page 401 Unit: mm 16.0 ± 0.2 *0.32 ± 0.08 0.13 M 0.30 ± 0.06 0.83 0° – 8° 0.5 ± 0.1 0.10 *Dimension including the plating thickness Base material dimension Figure F.2 TFP-80F Package Dimensions...
Page 402 14.0 ± 0.2 Unit: mm *0.22 ± 0.05 0.10 0.20 ± 0.04 1.25 0° – 8° 0.5 ± 0.1 0.10 *Dimension including the plating thickness Base material dimension Figure F.3 TFP-80C Package Dimensions...
Page 403 H8/3637 Series Hardware Manual Publication Date: 1st Edition, August 1998 Published by: Electronic Devices Business Group Hitachi, Ltd. Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.

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H8/3635 H8/3636

Hitachi H8/3637 Hardware Manual

Overview

Cpu

Exception Handling

Clock Pulse Generators

Power-Down Modes

Rom

Ram

I/O Ports

Timers

Section 10 Serial Communication Interface

Section 11 DTMF Generator

Section 12 A/D Converter

Section 13 14-Bit Pulse Width Modulator (PWM)

Section 14 Electrical Characteristics

Appendix A CPU Instruction Set

Appendix B On-Chip Registers

Appendix C I/O Port Block Diagrams

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Summary of Contents for Hitachi H8/3637