Fir Controller Register Description; Uart Register Of Fir Portion - Hitachi HD64465 User Manual

11.2

FIR Controller Register Description

11.2.1

UART Register of FIR Portion

The register has the same definition as that of UART, except that the address spaces are different.
Register DLAB* Address
Data 0 H'10007000 IrRBR (Receiver Buffer Register)
Control 0 H'10007002
x H'10007004
x H'10007006
x H'10007008
1 H'10007000
1 H'10007002
Status x H'1000700A
x H'1000700C
x H'1000700E
Note: DLAB* is bit 7 of the Line Control register (IrLCR).
Rev. 3.0, 03/01, page 132 of 390
READ
IrIER (Interrupt Enable Register)
IrIIR (Interrupt Identification Register)
IrLCR (Line Control Register)
IrMCR (Modem Control Register)
IrDLL (Divisor Latch LSB)
IrDLM (Divisor Latch MSB)
IrLSR (Line Status Register)
IrMSR (Modem Status Register)
IrSCR (Scratch Pad Register)
WRITE
IrTBR (Transmitter Buffer Register)
IrIER
IrFCR (FIFO Control Register)
IrLCR
IrMCR
IrDLL
IrDLM
IrLSR
IrMSR
IrSCR