14.2.19 Ac97 Tx Fifo Status Register - Hitachi HD64465 User Manual

AC97 Transmit Interrupt Enable Register (ATIER) [cont'd]
Bit Description
3 PCMLFE TX FIFO UNDERRUN Interrupt Enable (PLFETFUNIE):
When this bit is 1, PCMLFE TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, PCMLFE TX FIFO UNDERRUN Interrupt is disabled.
2 Line2 TX FIFO UNDERRUN Interrupt Enable (L2TFUNIE):
When this bit is 1, Line 2 TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, Line 2 TX FIFO UNDERRUN Interrupt is disabled.
1 HSET TX FIFO UNDERRUN Interrupt Enable (HTTFUNIE):
When this bit is 1, HSET TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, HSET TX FIFO UNDERRUN Interrupt is disabled.
IO CTRL TX FIFO UNDERRUN Interrupt Enable (IOCTFUNIE):
0
When this bit is 1, IO CTRL TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, IO CTRL TX FIFO UNDERRUN Interrupt is disabled.

14.2.19 AC97 TX FIFO Status Register

ATSR, a 32-bit Read Only register, is used to reflect the status of AC97 TX controller. Bits 31-30
are reserved. The other bits are initialized to 0 at reset. ATIER is not initialized in STANDBY
mode.
Bit 31
Bit Name -
Initial Value -
R/W -
Bit 23
Bit Name PLFETFR
Q
Initial Value 0
R/W R
Bit 15
Bit Name PLSTFO
V
Initial Value 0
R/W R
30 29 28
- PLTFRQ PRTFRQ L1TFRQ PCTFRQ PLSTFR
- 0 0
- R R
22 21 20
L2TFRQ HTTFRQ IOCTFRQ PLTFOV PRTFOV L1TFOV PCTFOV
0 0 0
R R R
14 13 12
PRSTFO PLFETFO L2TFOV HTTFOV IOCTFOV PLTFUN PRTFUN
V V
0 0 0
R R R
27 26 25
Q
0 0 0
R R R
19 18 17
0 0 0
R R R
11 10 9
0 0 0
R R R
Rev. 3.0, 03/01, page 205 of 390
Default
0
0
0
0
24
PRSTFR
Q
0
R
16
0
R
8
0
R