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Item
54
6.3.2 System Configuration
Register (SCONFR)
Description of Bits 11 - 8
58
6.3.4 System Peripheral Clock
Control Register (SPCCR)
59
Figure 6.1 AFECK & LCK
Related Clock Diagram
71
7.3.1 Port Data Register
91
Table 9.1 The Register List of
Timer Module
93
9.2.3 TRVR1:Timer 1 Read Vlue
Register
94
9.2.4 TRVR0:Timer 0 Read
Value Register
99
9.2.9 PWM1CS: PWM1 Clock
Scale Register
Bits 5 - 0
102
9.2.12 PWM0CS: PWM0 Clock
Scale Register
Bits 5 - 0
121
10.4.8 PCC1 General Control
Register (PCC1GCR)
Description
Add the following description
Note that the relationship between HW[3:0] and CPU
programmed inserted wait states (IWS) is 2 ≤ 1 WS ≤
1+HW[3:0]. Hence, the CPU default inserted wait
states should be 2.
<Former Edition>
Note: The parameter, Twkst, please refer the AC
timing specification.
<This Edition>
Note: The parameter, Twkst = 15 ms
Add the description ofACCLK pin
<Former Edition>
GPCDR -- Address: 100004018h
<This Edition>
GPEDR -- Address: H'100004018
<Former Edition>
Register Size = 2
Access Size = 2
<This Edition>
Register Size = 16
Access Size = 16
<Former Edition> R/W value = R/O
<This Edition> R/W value = R
Delete the default value
Description of bit 7
<Former Edition> PCC0
<This Edition> PCC1
Description of bit 4
<Former Edition> VCC0SEL1
<This Edition> VCC1SEL0
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