Table of Contents
Advertisement
9.1.3
Pin Configuration
Name
Abbr.
Timer 1 output
TMO1#
Timer 0 output
TMO0#
DMA request
DREQ1#
PWM 1 output
PWM1
PWM 0 output
PWM0
9.1.4
Register Configuration
The timer contains seven registers listed in the table below:
Table 9.1
The Register List of Timer Module
Name
Timer 1 constant value register (TCVR1)
Timer 0 constant value register (TCVR0)
Timer 1 read value register (TRVR1)
Timer 0 read value register (TRVR0)
Timer 1 control register (TCR1)
Timer 0 control register (TCR0)
Timer interrupt request register (TIRR)
Timer interrupt disable register (TIDR)
PWM 1 clock scale register (PWM1CS)
PWM 1 low pulse width counter register
(PWM1LPC)
PWM 1 high pulse width counter register
(PWM1HPC)
PWM 0 clock scale register (PWM0CS)
PWM 0 low pulse width counter register
(PWM0LPC)
PWM 0 high pulse width counter register
(PWM0HPC)
I/O
Description
O
Multiplexed with PB1/TMO1#. Timer output signal is enabled
by bit 3 ETMO1 in Timer 1 Control register TCR1.
O
Multiplexed with PB0/TMO0#. Timer output signal is enabled
by bit 3 ETMO0 in Timer 0 Control register TCR0.
O
DMA request.
O
PWM channel 1 output
O
PWM channel 0 output
Address
H'10006000
H'10006002
H'10006004
H'10006006
H'10006008
H'1000600A
H'1000600C
H'1000600E
H'10006010
H'10006012
H'10006014
H'10006018
H'1000601A
H'1000601C
Register Size
Access Size
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Rev. 3.0, 03/01, page 91 of 390
Advertisement
Table of Contents
