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Figure 15-3. HC1 Pin and Control Data Outputs .........................................................................240
Figure 15-4. TDEI Output Timing ...............................................................................................241
Figure 15-5. RDFI Output Timing ...............................................................................................242
Figure 16-1. H8 Keyboard Controller Interface Block Diagram..................................................244
Figure 16-2. Keyboard Controller Interface Read Timing ...........................................................247
Figure 16-3. Keyboard Controller Interface Write Timing ..........................................................247
Figure 17-1. PS/2 Keyboard/Mouse Interface Block Diagram ....................................................254
Figure 17-2. Keyboard Serial Data Format ..................................................................................255
Figure 17-3. Data Receive Timing...............................................................................................257
Figure 17-4. Data Send Timing....................................................................................................258
Figure 18-1. USB States...............................................................................................................261
Figure 18-2. List Priority within a USB Frame............................................................................264
Figure 18-3. Example of Control/Bulk Service Ratio of 4:1........................................................265
Figure 18-4. List Service Flow.....................................................................................................268
Figure 18-5. Endpoint Descriptor Service Flow ..........................................................................271
Figure 18-6. Endpoint Descriptor ................................................................................................273
Figure 18-7. Transfer Description Service Flow..........................................................................274
Figure 18-8. Standard Token Packet Format................................................................................296
Figure 18-9. SOF Token Packet Format ......................................................................................296
Figure 18-10. Data Packet Format ...............................................................................................297
Figure 18-11. Handshake Packet Format .....................................................................................297
Figure 18-12. Preamble Packet Format........................................................................................298
Figure 18-13. Serializer................................................................................................................299
Figure 18-14. CRC Logic.............................................................................................................300
Figure 18-15. Non-Isochronous Bus Transaction ........................................................................304
Figure 18-16. Isochronous Bus Transaction.................................................................................305
Figure 19-1. A/D Converter Block Diagram................................................................................334
(Scan Mode, Channels An0 to AN2 Selected)........................................................342
Figure 19-4. A/D Conversion Timing ..........................................................................................343
Figure 19-5. External Trigger Input Timing ................................................................................344
Figure 19-6. Analog Input Pin RC Equivalent Circuit .................................................................346
Figure 20-1. CPU Write Cycle Timing Diagram .........................................................................354
Figure 20-2. CPU Read Cycle Timing Diagram ..........................................................................354
Figure 20-3. Crystal/Oscillator and PLL Settle Timing Diagrams...............................................355
Figure 20-4. I/O Port Interrupt Timing (Falling Edge Trigger) ...................................................355
Figure 20-5. I/O Port Interrupt Timing (Rising Edge Trigger) ....................................................356
Figure 20-6. IRQ0#/TMO0# Timing For Timer ..........................................................................356
Figure 20-7. IRQ0#/TMO1# Timing For Timer ..........................................................................356
Figure 20-8. DREQ0# / DREQ1# Timing ...................................................................................356
Figure 20-9. PCMCIA I/O Bus Cycle (NO Wait)........................................................................357
Figure 20-10. PCMCIA Memory Bus Cycle (No Wait) ..............................................................358
Rev. 3.0, 03/01, page xii of xiii
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