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The Bus Master Controller maintains the address of the next PCI cycle to be requested. The
address is initialized with a value from the List Processor when it initiates a request. The address is
updated after each burst transfer completes. This is needed for data transfers that require more than
a single burst cycle.
Data Buffer Engine
The Data Buffer Engine controls the bus master requests for transferring data to and from the Data
Buffer. The Data Buffer Engine monitors the status of the Data Buffer by using the SIE pointer and
the PCI pointer. These pointers indicate the next location to be read from or written to by the SIE
data and the PCI data respectively. When the Data Buffer Engine determines that there is space
available in the Data Buffer, it makes a request to the Page Crossing Controller that a bus master
cycle be initiated.
The Data Buffer is divided into either two 32-byte or four 16-byte regions, depending on the value
of the DataBufferRegion16 bit in the PCI configuration register OperationalMode. Whenever the
PCI pointer is not in the same region as the SIE pointer, there is sufficient room in the Data Buffer
to transfer at least one region worth of data. Once a transfer request has been issued, the size of the
transfer will not change, even if more data becomes available in the buffer before the PCI
Controller services the request.
If the region size is 32, then there are 32 bytes available in the buffer while a PCI Master cycle is in
progress. The maximum PCI latency that can be tolerated without losing Isochronous data is:
32 bytes avail * 8 clocks/byte * 83.33 ns/clock = 21,333 ns
If the region size is 16, then there can be between 16 to 48 bytes available in the buffer for SIE data
while a PCI Master cycle is in progress. Initially there are three regions available for SIE data
while one region is being transferred on PCI. If the SIE transfers data in the three regions before
the PCI transfer completes, then only one region is available for SIE data during the next PCI
transfer. The maximum PCI latency that can be tolerated without losing Isochronous data ranges
from:
16 bytes avail * 8 clocks/byte * 83.33 ns/clock = 10,666 ns
32 bytes avail * 8 clocks/byte * 83.33 ns/clock = 21,333 ns
48 bytes avail * 8 clocks/byte * 83.33 ns/clock = 32,000 ns
The region size of 16 is advantageous for a Most Recently Used type PCI arbitration scheme where
the initial grant may require up to 32,000 ns but the subsequent grant occurs within 10,666 ns
Rev. 3.0, 03/01, page 292 of 390
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