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19.3.2
Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs of one or more channels. When the ADST bit is
set to 1 by software or external trigger input, A/D conversion starts on the first channel (AN0).
When two or more channels are selected, the conversion of the second channel (AN1) starts
immediately after the first channel finishes the conversion. The A/D conversion continues in cycles
on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred
for storage into the A/D data registers in correspondences with the selected channels.
When the mode or analog input channel selection must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1. The A/D conversion will then start again
from the first channel. The ADST bit can be set at the same time when the mode or channel
selection is changed.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
next. Figure 19-3 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), analog input channels AN0 to AN2 are selected (CH1 = 1,
CH0 = 0), and A/D conversion is started (ADST = 1).
2. When A/D conversion of the first channel (AN0) is completed, the conversion result is
transferred into ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI
interrupt is requested at this time.
Steps 2 to 4 are repeated as long as the ADST bit value remains at 1. When the ADST bit is cleared
to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from
the first channel (AN0).
ADCSR (SCAN = 1)
CH1
0
0
1
1
CH0
0
1
0
1
ANn
AN0
AN0 to AN1
AN0 to AN2
AN0 to AN3
Rev. 3.0, 03/01, page 341 of 390
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