Operation; Single Mode (Scan = 0) - Hitachi HD64465 User Manual

Windows ce intelligent peripheral controller
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19.3

Operation

The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
19.3.1

Single Mode (SCAN = 0)

Single mode should be selected when only one A/D conversion in one channel is required. The
A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The
ADST bit value remains at 1 during the A/D conversion and is automatically cleared to 0 when the
conversion ends.
When the conversion ends, the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt
is requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.
When the mode or analog input channel must be switched during the analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making
the required changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set
at the same time when the mode or channel is being changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next.
Figure 19-2 shows a timing diagram for this example.
1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH1= 0, CH0 = 1), the
A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time
when the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes
idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The routine reads ADCSR, then writes 0 in the ADF flag, and writes 0 in ADIS flag to reset
interrupt.
6. The routine reads and processes the conversion result (ADDRB).
The execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 6 are repeated.
Rev. 3.0, 03/01, page 339 of 390

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