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14.2.6
Command/Status Address Register (CSAR)
CSAR, a 32-bit Read/Write register, is a channel via which the system can write command address
to CODEC or read status address from CODEC. Bits 31-20 and bits 11-0 are reserved. The other
bits are initialized to 0 at reset. CAR is not initialized in STANDBY mode.
Bit
31
Bit Name
-
Initial Value
-
R/W
-
Bit
23
Bit Name
-
Initial Value
-
R/W
-
Bit
15
Bit Name
CA3/SA3 CA2/SA2 CA1/SA1 CA0/SA0 -
Initial Value
0
R/W
R/W
Bit
7
Bit Name
-
Initial Value
0
R/W
-
Bit
Description
31 - 20
Reserved
19
Read/Write Command (RW)
1=read, 0=write
18 - 12
Control Register Address 6-0 (CA6-CA0)/Status Address 6-0 (SA6-SA0):
When this register is written, these bits are control register address. Control register has
64 16-bit locations, addressed on even byte boundaries.
When this register is read, these bits are the address of the register which data is being
returned.
11 - 0
Reserved
Rev. 3.0, 03/01, page 190 of 390
30
29
28
-
-
-
-
-
-
-
-
-
22
21
20
-
-
-
-
-
-
-
-
-
14
13
12
0
0
0
R/W
R/W
R/W
6
5
4
-
-
-
0
0
0
-
-
-
27
26
25
-
-
-
-
-
-
-
-
-
19
18
17
RW
CA6/SA6 CA5/SA5 CA4/SA4
0
0
0
R/W
R/W
R/W
11
10
9
-
-
0
0
0
-
-
-
3
2
1
-
-
-
0
0
0
-
-
-
24
-
-
-
16
0
R/W
8
-
0
-
0
-
0
-
Default
-
0
0
0
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