Status Model Diagrams - Keithley 708B Reference Manual

Models 707B and 708B Switching Matrix Reference Manual
Summary bit
The summary bit of each register is either set (1) or clear (0). A set summary bit indicates that one (or
more) of the enabled events in that register has occurred.
Queues
The Switching Matrix uses an Output queue and an Error or Event queue. Response messages, such
as those generated from print commands, are placed in the Output Queue. As programming errors
and status messages occur, they are placed in the Error queue. When a queue contains data, it sets
the appropriate summary bit of the Status Byte Register (EAV for the Error or Event queue; MAV for
the Output queue).
The Status Byte register overview
other registers.
Output queue
When the instrument is in the remote state, the output queue holds data that pertains to the normal
operation of the instrument. For example, when a print() command is sent, the response message
is placed in the output queue.
When data is placed in the output queue, the Message Available (MAV) bit in the status byte register
is set. A response message is cleared from the output queue when it is read. The output queue is
considered cleared when it is empty. An empty output queue clears the MAV bit in the status byte
register.
A message is read from the output queue by addressing the instrument to talk.

Status model diagrams

The register sets (and queues) monitor various instrument events. When an enabled event occurs in
one of the five registers, it sets the associated summary bit in the Status Byte register. When a
summary bit of the Status Byte is set and its corresponding enable bit is set (as programmed using
status.request_enable), the MSS bit will set to indicate that an SRQ has occurred. View the
master summary bit using status.condition attribute. In an expanded system (TSP-link), setting
the status.node_enable attribute allows the System registers to be shared by all nodes in the
TSP-Link system. The following figures and topics illustrate the relationships of the individual registers
and queues with the Status Byte register.
707B-901-01 Rev. A / August 2010
(on page C-4) shows how the two queues are structured with the
Appendix C: Status model
C-3