Keithley 708B Reference Manual page 438

Models 707B and 708B Switching Matrix Reference Manual
The individual bits of the status byte condition register can be set using constants (for example, to set the enable
bit of the status register to B0, set status.request_enable = status.MSB). The following table contains
descriptions of the bits and available values:
Bit Value
B0 status.MEASUREMENT_SUMMARY_BIT
status.MSB
B1 status.SYSTEM_SUMMARY_BIT
status.SSB
B2 status.ERROR_AVAILABLE
status.EAV
B3
status.QUESTIONABLE_SUMMARY_BIT
status.QSB
B4 status.MESSAGE_AVAILABLE
status.MAV
B5 status.EVENT_SUMMARY_BIT
status.ESB
B6 Not used.
B7
status.OPERATION_SUMMARY
status.OSB
In addition to the above values, requestSRQEnableRegister can be set to the decimal equivalent of the bit to
set. To set more than one bit of the register, set requestSRQEnableRegister to the sum of their decimal
weights. For example, to set bits B0 and B7, set requestSRQEnableRegister to 129 (1 + 128).
Bit
Binary value
Decimal
Weights
Example 1
requestSRQEnableRegister = status.MSB +
status.OSB
status.request_enable = requestSRQEnableRegister
Example 2
-- decimal 129 = binary 10000001
requestSRQEnableRegister = 129
status.request_enable = requestSRQEnableRegister
Also see
status.condition
status.system.*
Status byte and service request (SRQ)
707B-901-01 Rev. A / August 2010
B7 B6
0/1 0/1
128 64
7 6
(2 ) (2 )
(on page 7-173)
(on page 7-190)
(on page C-15)
Description
Set summary bit indicates that an enabled measurement
event has occurred.
Bit 0 decimal value: 1
Set summary bit indicates that an enabled system
event has occurred.
Bit 1 decimal value: 2
Set summary bit indicates that an error or status message
is present in the Error Queue.
Bit 2 decimal value: 4
Set summary bit indicates that an enabled questionable
event has occurred.
Bit 3 decimal value: 8
Set summary bit indicates that a response message is
present in the Output Queue.
Bit 4 decimal value: 16
Set summary bit indicates that an enabled standard event
has occurred.
Bit 5 decimal value: 32
Not applicable.
Set summary bit indicates that an enabled operation event
has occurred.
Bit 7 decimal value: 128
B5 B4 B3
0/1 0/1 0/1
32 16 8
5 4 3
(2 ) (2 ) (2 )
Sets the MSB and OSB bits of the
request SRQ enable register using
constants.
Sets the MSB and OSB bits of the
request SRQ enable register using a
decimal value.
Section 7: Command reference
B2 B1 B0
0/1 0/1 0/1
4 2 1
2 1 0
(2 ) (2 ) (2 )
7-185