Mpc821 To S1D13706 Interface; Hardware Description - Epson S1D13706 Technical Manual

Embedded memory lcd controller

Hide thumbs Also See for S1D13706:

Table of Contents

Epson Research and Development

Vancouver Design Center

4 MPC821 to S1D13706 Interface

When connecting the S1D13706 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

Figure 4-1: Typical Implementation of MPC821 to S1D13706 Interface

Interfacing to the Motorola MPC821 Microprocessor

Issue Date: 01/02/23

The interface between the S1D13706 and the MPC821 requires no external glue logic. The

polarity of the WAIT# signal must be selected as active high by connecting CNF5 to NIO

(see Table 4-2:, "Summary of Power-On/Reset Configuration Options," on page 18).

BS# (bus start) is not used in this implementation and should be tied high (connected to

The following diagram shows a typical implementation of the MPC821 to S1D13706

Table 4-1:, "List of Connections from MPC821ADS to S1D13706" on page 16 shows the

connections between the pins and signals of the MPC821 and the S1D13706.

System RESET

X31B-G-009-02

Table of Contents