Overview Of Xreg Registers - Texas Instruments CC253x User Manual

Memory
XREG Registers. The XREG registers are additional registers in the XDATA memory space. These
registers are mainly used for radio configuration and control. For more details regarding each register, see
the corresponding module or peripheral chapter.
address space.
XDATA Address
0x6000–0x61FF
0x61A6
0x61AD
0x6200–0x622B
0x6230
0x6231
0x6232
0x6233
0x6234
0x6235
0x6243
0x6244
0x6245
0x6246
0x6247
0x6248
0x6249
0x624A
0x624B
0x6260
0x6262
0x6264
0x6265
0x6270
0x6271
0x6272
0x6273
0x6276
0x6277
0x6281
0x6290
0x62A0
0x62A1
0x62A2
0x62A3
0x62A4
0x62A6
0x62A7
32
8051 CPU
Table 2-2. Overview of XREG Registers
Register Name
Radio registers (see CC253x Radio
— Radio Section 24.1
complete list)
MONMUX Battery monitor MUX (CC2533)
OPAMPMC Operational amplifier mode control (CC2530, CC2531)
OPAMPMC Operational amplifier mode control (CC2540)
— USB registers (see
2
I2CCFG I C control
2
I2CSTAT I C status
2
I2CDATA I C data
2
I2CADDR I C own slave address
I2CWC Wrapper control
I2CIO GPIO
OBSSEL0 Observation output control register 0
OBSSEL1 Observation output control register 1
OBSSEL2 Observation output control register 2
OBSSEL3 Observation output control register 3
OBSSEL4 Observation output control register 4
OBSSEL5 Observation output control register 5
CHVER Chip version
CHIPID Chip identification
TR0 Test register 0
DBGDATA Debug interface write data
SRCRC Sleep reset CRC
BATTMON Battery monitor
IVCTRL Analog control register
FCTL Flash control
FADDRL Flash address low
FADDRH Flash address high
FWDATA Flash write data
CHIPINFO0 Chip information byte 0
CHIPINFO1 Chip information byte 1
IRCTL Timer 1 IR generation control
CLD Clock-loss detection
Timer 1 channel 0 capture or compare control (additional XREG
T1CCTL0
mapping of SFR register)
Timer 1 channel 1 capture or compare control (additional XREG
T1CCTL1
mapping of SFR register)
Timer 1 channel 2 capture or compare control (additional XREG
T1CCTL2
mapping of SFR register)
T1CCTL3 Timer 1 channel 3 capture or compare control
T1CCTL4 Timer 1 channel 4 capture or compare control
Timer 1 channel 0 capture or compare value low (additional
T1CC0L
XREG mapping of SFR register)
Timer 1 channel 0 capture or compare value high (additional
T1CC0H
XREG mapping of SFR register)
Copyright © 2009–2014, Texas Instruments Incorporated
Table 2-2 gives a descriptive overview of the register
Description
Section 23.15
or CC2541 Radio Section 25.12
Section 21.12 for complete list)
SWRU191F – April 2009 – Revised April 2014
www.ti.com
or CC2540
for
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