Aes Interrupts; Aes Dma Triggers; Aes Registers - Texas Instruments CC253x User Manual

AES Interrupts

Message Decryption
CCM Mode Decryption
In the coprocessor, the automatic generation of CTR works on 32 bits; therefore, the maximum length of a
message is 128 × 2
To decrypt a CCM-mode processed message, the following sequence can be conducted (key is already
loaded).
Message Parsing Phase
1. The software parses the message by separating the M rightmost octets, namely U, and the other
octets, namely string C.
2. C is padded with zeros until it can fill an integral number of 128-bit blocks.
3. U is padded with zeros until it can fill a 128-bit block.
4. The software creates the key stream block A0. It is done the same way as for CCM encryption.
5. The software loads A0 by selecting a Load IV/nonce command. To do so, it sets the mode to CFB or
OFB at the same time as it selects the IV load.
6. The software calls a CFB or an OFB encryption on the encrypted authenticated data U. The uploaded
buffer contents stay unchanged (M = 16), or only its first M bytes stay unchanged, the others being set
to 0 (M != 16). The result is T.
7. The software calls a CTR-mode decryption immediately on the encrypted message blocks C.
Reloading the IV/CTR is not necessary.
Reference Authentication Tag Generation
This phase is identical to the authentication phase of CCM encryption. The only difference is that the
result is named MACTag (instead of T).
Message Authentication Checking Phase
The software compares T with MACTag.
15.8 AES Interrupts
The AES interrupt, ENC, is produced when encryption or decryption of a block is completed. The interrupt
enable bit is IEN0.ENCIE, and the interrupt flag is S0CON.ENCIF.

15.9 AES DMA Triggers

Two DMA triggers are associated with the AES coprocessor. These are ENC_DW, which is active when
input data must be downloaded to the ENCDI register, and ENC_UP, which is active when output data
must be uploaded from the ENCDO register.
The ENCDI and ENCDO registers should be set as destination and source locations for DMA channels
used to transfer data to or from the AES coprocessor.

15.10 AES Registers

The AES coprocessor registers have the layout shown in this section.
The registers return to their reset value when the chip enters PM2 or PM3.
150
AES Coprocessor
32 36
bits, that is 2 bytes, which can be written in a 6-bit word. So, the value L is set to 6.
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SWRU191F – April 2009 – Revised April 2014
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