Clock Rates Defined At 32 Mhz - Texas Instruments CC253x User Manual

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2
I2CCFG (0x6230) – I C Control
Bit Name Reset
7 CR2 0
6 0
ENS1
5 STA 0
4 STO 0
3 SI 0
2 AA 0
1 CR1 0
0 CR0 0
CR2
0
0
0
0
1
1
1
1
2
I2CSTAT (0x6231) – I C Status
Bit Name Reset
7:3 STAC 1111 1
2:0 – 000
2
I2CDATA (0x6232) – I C Data
Bit Name Reset
7:0 SD 0000 00 R/W
00
2
I2CADDR (0x6233) – I C Own Slave Address
Bit Name Reset
7:1 ADDR 0000 00 R/W
0
0 GC 0
SWRU191F – April 2009 – Revised April 2014
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R/W Description
R/W Clock rate bit 2
R/W Enable bit
2
0: I C module disabled
SCL and SDA are set to high-impedance inputs. The inputs are ignored by the I
module.
Note that setting ENS1 = 0 disables the I
2
1: I C module enabled
R/W START flag. When set, HW detects when I
R/W1 STOP flag. When set and in master mode, a STOP condition is transmitted on the I
HW is cleared when transmit has completed successfully.
R/W0 Interrupt flag
R/W Assert acknowledge flag for the I
When set (AA = 1), an acknowledge is returned when:
● Slave address is recognized
● General call is recognized, when the I
● Data byte received while in master or slave receive mode
When not set (AA = 0), an acknowledge is returned when:
● Data byte is received while in master or slave receive mode
R/W Clock rate bit 1
R/W Clock rate bit 0
Table 20-6. Clock Rates Defined at 32 MHz
Bit Frequency
CR1 CR0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
R/W Description
R Status code. Contains the state of the I
Interrupt is only requested when in states 0 to 25.
The value 0xF8 indicates that there is no relevant state information available and that
I2CCFG.SI = 0.
R0 Reserved
R/W Description
Serial data in/out (MSB is bit 7, LSB is bit 0). Contains data byte to be transmitted or byte
which has just been received. Can be read or written while not in the process of shifting a
byte. The register is not shadowed or double buffered, so it should only be accessed on an
interrupt.
R/W Description
Own slave address
R/W General-call address acknowledge. If set, the general-call address is recognized.
Copyright © 2009–2014, Texas Instruments Incorporated
2
C is free and generates a START condition.
2
C module.
2
C module is enabled
(kHz)
123
144
165
197
33
267
533
Reserved
2
C core. 27 states are defined: 0 to 25 and 31.
2
I C Registers
2
C module but does not reset its state.
Clock Divided by
256
244
192
160
960
120
60
N/A
2
C
2
C bus.
179
2
I C