Cpu Memory Space - Texas Instruments CC253x User Manual

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0 xFFFF
Bank 0–7
(32KB FLASH)
0x 8000
0x7FFF
Common Area/Bank 0
(32KB FLASH)
0x 0000
Figure 2-2. CODE Memory Space

2.2.2 CPU Memory Space

XDATA memory space. The XDATA memory map is given in
The SRAM is mapped into address range of 0x0000 through (SRAM_SIZE – 1).
The XREG area is mapped into the 1 KB address range (0x6000–0x63FF). These registers are additional
registers, effectively extending the SFR register space. Some peripheral registers and most of the radio
control and data registers are mapped in here.
The SFR registers are mapped into address range (0x7080–0x70FF).
The flash information page (2 KB) is mapped into the address range (0x7800–0x7FFF). This is a read-only
area and contains various information about the device.
The upper 32 KB of the XDATA memory space (0x8000–0xFFFF) is a read-only flash code bank (XBANK)
and can be mapped to any of the available flash banks using the MEMCTR.XBANK[2:0] bits.
The mapping of flash memory, SRAM, and registers to XDATA allows the DMA controller and the CPU
access to all the physical memories in a single unified address space.
Writing to unimplemented areas in the memory map (shaded in the figure) has no effect. Reading from
unimplemented areas returns 0x00. Writes to read-only regions, that is, flash areas, are ignored.
CODE memory space. The CODE memory space is 64 KB and is divided into a common area
(0x0000–0x7FFF) and a bank area (0x8000–0xFFFF) as shown in
always mapped to the lower 32 KB of the physical flash memory (bank 0). The bank area can be mapped
to any of the available 32-KB flash banks (from 0 to 7). The number of available flash banks depends on
the flash size option. Use the flash-bank-select register, FMAP, to select the flash bank. On 32-KB
devices, no flash memory can be mapped into the bank area. Reads from this region return 0x00 on these
devices.
To allow program execution from SRAM, it is possible to map the available SRAM into the lower range of
the bank area from 0x8000 through (0x8000 + SRAM_SIZE – 1). The rest of of the currently selected bank
is still mapped into the address range from (0x8000 + SRAM_SIZE) through 0xFFFF). Set the
MEMCTR.XMAP bit to enable this feature.
DATA memory space. The 8-bit address range of DATA memory is mapped into the upper 256 bytes of
the SRAM, that is, the address range from (SRAM_SIZE – 256) through (SRAM_SIZE – 1).
SWRU191F – April 2009 – Revised April 2014
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M0098-02
Figure 2-3. CODE Memory Space for Running Code
Copyright © 2009–2014, Texas Instruments Incorporated
0 xFFFF
Banks 0–7
(Upper 24KB FLASH)
0x8000 + SRAM_SIZE
0x8000 + SRAM_SIZE – 1
SRAM
0x 8000
0x7FFF
Common Area/Bank 0
(32KB FLASH)
0x 0000
From SRAM
Figure 2-1.
Figure 2-2. The common area is
Memory
M0099-04
27
8051 CPU