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2.1
8051 CPU Introduction
The enhanced 8051 core uses the standard 8051 instruction set. Instructions execute faster than the
standard 8051 due to the following:
•
One clock per instruction cycle is used as opposed to 12 clocks per instruction cycle in the standard
8051.
•
Wasted bus states are eliminated.
Because an instruction cycle is aligned with memory fetch when possible, most of the single-byte
instructions are performed in a single clock cycle. In addition to the speed improvement, the enhanced
8051 core also includes architectural enhancements:
•
A second data pointer
•
An extended 18-source interrupt unit
The 8051 core is object-code-compatible with the industry-standard 8051 microcontroller. That is, object
code compiled with an industry-standard 8051 compiler or assembler executes on the 8051 core and is
functionally equivalent. However, because the 8051 core uses a different instruction timing than many
other 8051 variants, existing code with timing loops may require modification. Also, because the peripheral
units such as timers and serial ports differ from those on other 8051 cores, code which includes
instructions using the peripheral-unit SFRs does not work correctly.
Flash prefetching is not enabled by default, but improves CPU performance by up to 33%. This is at the
expense of slightly increased power consumption, but in most cases improves energy consumption as it is
faster. Flash prefetching can be enabled in the FCTL register.
2.2
Memory
The 8051 CPU architecture has four different memory spaces. The 8051 has separate memory spaces for
program memory and data memory. The 8051 memory spaces are the following (see
Section 2.2.2
for details):
CODE. A read-only memory space for program memory. This memory space addresses 64 KB.
DATA. A read-or-write data memory space that can be directly or indirectly accessed by a single-cycle
CPU instruction. This memory space addresses 256 bytes. The lower 128 bytes of the DATA memory
space can be addressed either directly or indirectly, the upper 128 bytes only indirectly.
XDATA. A read-and-write data memory space, access to which usually requires 4–5 CPU instruction
cycles. This memory space addresses 64 KB. Access to XDATA memory is also slower than DATA
access, as the CODE and XDATA memory spaces share a common bus on the CPU core, and instruction
prefetch from CODE thus cannot be performed in parallel with XDATA accesses.
SFR. A read-or-write register memory space which can be directly accessed by a single CPU instruction.
This memory space consists of 128 bytes. For SFR registers whose address is divisible by eight, each bit
is also individually addressable.
The four different memory spaces are distinct in the 8051 architecture, but are partly overlapping in the
device to ease DMA transfers and hardware debugger operation.
How the different memory spaces are mapped onto the three physical memories (flash program memory,
SRAM, and memory-mapped registers) is described in
2.2.1 Memory Map
The memory map differs from the standard 8051 memory map in two important aspects, as described in
the following paragraphs.
First, in order to allow the DMA controller access to all physical memory and thus allow DMA transfers
between the different 8051 memory spaces, parts of SFR and the DATA memory space are mapped into
the XDATA memory space (see
Second, two alternative schemes for CODE memory space mapping can be used. The first scheme is the
standard 8051 mapping where only the program memory (that is, flash memory) is mapped to CODE
memory space. This mapping is the default after a device reset and is shown in
SWRU191F – April 2009 – Revised April 2014
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Figure
2-1).
Copyright © 2009–2014, Texas Instruments Incorporated
Section 2.2.1
and
Section
8051 CPU Introduction
Section 2.2.1
and
2.2.2.
Figure
2-2.
25
8051 CPU
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