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P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to Port 0. When set to
01, USART 1 has precedence. Note that if UART mode is selected and hardware flow control is disabled,
USART 0 or Timer 1 has precedence to use ports P0.2 and P0.3.
P2SEL.PRI3P1 and P2SEL.PRI2P1 select the order of precedence when assigning several peripherals
to Port 1. USART 1 has precedence when the former is set to 1 and the latter is set to 0. Note that if
UART mode is selected and hardware flow control is disabled, USART 0 or Timer 3 has precedence to
use ports P1.4 and P1.5.
7.6.6 ADC
In
Table
7-1, the ADC signals are shown as follows:
•
A0: ADC input 0
•
A1: ADC input 1
•
A2: ADC input 2
•
A3: ADC input 3
•
A4: ADC input 4
•
A5: ADC input 5
•
A6: ADC input 6
•
A7: ADC input 7
•
T: ADC external trigger pin
When using the ADC, Port 0 pins must be configured as ADC inputs. Up to eight ADC inputs can be used.
To configure a Port 0 pin to be used as an ADC input, the corresponding bit in the APCFG register must be
set to 1. The default values in this register select the Port 0 pins as non-ADC input, i.e., digital
input/outputs.
The settings in the APCFG register override the settings in P0SEL.
The ADC can be configured to use the general-purpose I/O pin P2.0 as an external trigger to start
conversions. P2.0 must be configured as a general-purpose I/O in input mode when being used for ADC
external trigger.
7.6.7 Operational Amplifier and Analog Comparator
When using the operational amplifier and analog comparator, the corresponding Port 0 pins must be
configured as ADC inputs (see
corresponding bit in the APCFG register must be set to 1. The default values in this register select the Port
0 pins as non-ADC input, that is, digital input/outputs.
The settings in the APCFG register override the settings in P0SEL.
7.7
Debug Interface
Ports P2.1 and P2.2 are used for debug data and clock signals, respectively. These are shown as DD
(debug data) and DC (debug clock) in
direction of these pins. Pullup and pulldown are disabled on these pins while in debug mode.
7.8
32-kHz XOSC Input
Ports P2.3 and P2.4 can be used to connect an external 32-kHz crystal. These port pins are used by the
32-kHz XOSC when CLKCONCMD.OSC32K is low, regardless of register settings. The port pins are set in
analog mode when CLKCONCMD.OSC32K is low.
SWRU191F – April 2009 – Revised April 2014
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Table
7-1). To configure a Port 0 pin to be used as an ADC input, the
Table
7-1. When in debug mode, the debug interface controls the
Copyright © 2009–2014, Texas Instruments Incorporated
Peripheral I/O
83
I/O Ports
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