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Endpoint-0 Interrupts
21.6.1 Error Conditions
When a protocol error occurs, the USB controller sends a STALL handshake. The USBCS0.SENT_STALL
bit is asserted, and an interrupt request is generated if the endpoint-0 interrupt is properly enabled. A
protocol error can be any of the following:
•
An OUT token is received after USBCS0.DATA_END has been set to complete the OUT data stage (the
host tries to send more data than expected).
•
An IN token is received after USBCS0.DATA_END has been set to complete the IN data stage (the host
tries to receive more data than expected).
•
The USB host tries to send a packet that exceeds the maximum packet size during the OUT data
stage.
•
The size of the DATA1 packet received during the status stage is not 0.
The firmware can also terminate the current transaction by setting the USBCS0.SEND_STALL bit to 1. The
USB controller then sends a STALL handshake in response to the next request from the USB host.
If an EP0 interrupt is caused by the assertion of the USBCS0.SENT_STALL bit, this bit should be de-
asserted, and firmware should consider the transfer as aborted (and consequently free the memory
buffers, and so forth).
If EP0 receives an unexpected token during the data stage, the USBCS0.SETUP_END bit is asserted, and
an EP0 interrupt is generated (if enabled properly). EP0 then switches to the IDLE state. Firmware should
then set the USBCS0.CLR_SETUP_END bit to 1 and abort the current transfer. If USBCS0.OUTPKT_RDY is
asserted, this indicates that another setup packet has been received that firmware should process.
21.6.2 SETUP Transactions (IDLE State)
The control transfer consists of two or three stages of transactions (setup – data – status or setup –
status). The first transaction is a setup transaction. A successful setup transaction comprises three
sequential packets (a token packet, a data packet, and a handshake packet), where the data field
(payload) of the data packet is exactly 8 bytes long and is referred to as the setup packet. In the setup
stage of a control transfer, EP0 is in the IDLE state. The USB controller rejects the data packet if the
setup packet is not 8 bytes. Also, the USB controller examines the contents of the setup packet to
determine whether or not there is a data stage in the control transfer. If there is a data stage, EP0
switches state to TX (IN transaction) or RX (OUT transaction) when the USBCS0.CLR_OUTPKT_RDY bit is
set to 1 (if USBCS0.DATA_END = 0).
When a packet is received, the USBCS0.OUTPKT_RDY bit is asserted and an interrupt request is
generated (EP0 interrupt) if the interrupt has been enabled. Firmware should perform the following when a
setup packet has been received:
1. Unload the setup packet from the EP0 FIFO
2. Examine the contents and perform the appropriate operations
3. Set the USBCS0.CLR_OUTPKT_RDY bit to 1. This denotes the end of the setup stage. If the control
transfer has no data stage, the USBCS0.DATA_END bit must also be set. If there is no data stage, the
USB controller stays in the IDLE state.
21.6.3 IN Transactions (TX State)
If the control transfer requires data to be sent to the host, the setup stage is followed by one or more IN
transactions in the data stage. In this case, the USB controller is in the TX state and only accepts IN
tokens. A successful IN transaction comprises two or three sequential packets (a token packet, a data
packet, and a handshake packet
must be split into a number of 32-byte packets followed by a residual packet. If the number of bytes to
send is a multiple of 32, the residual packet is a zero-length data packet, because a packet size less than
32 bytes denotes the end of the transfer.
(1)
For isochronous transfers there would not be a handshake packet from the host.
184
USB Controller
). If more than 32 bytes (maximum packet size) is to be sent, the data
(1)
Copyright © 2009–2014, Texas Instruments Incorporated
SWRU191F – April 2009 – Revised April 2014
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