Dma Configuration-Data Structure - Texas Instruments CC253x User Manual

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DMA Trigger
Number Name
12 IOC_0
13 IOC_1
14 URX0
15 UTX0
16 URX1
17 UTX1
18 FLASH
19 RADIO
20 ADC_CHALL
21 ADC_CH11
22 ADC_CH21
23 ADC_CH32
24 ADC_CH42
25 ADC_CH53
26 ADC_CH63
27 ADC_CH74
28 ADC_CH84
29 ENC_DW
30 ENC_UP
31 DBG_BW
(1)
Using this trigger source must be aligned with port interrupt-enable bits. Note that all interrupt-enabled port pins generate a
trigger.
Byte
Bit
Offset
0 7:0 SRCADDR[15:8]
1 7:0 SRCADDR[7:0]
2 7:0
DESTADDR[15:8]
3 7:0
DESTADDR[7:0]
4 7:5 VLEN[2:0]
4 4:0 LEN[12:8]
SWRU191F – April 2009 – Revised April 2014
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Table 8-1. DMA Trigger Sources (continued)
Functional Unit
I/O controller
I/O controller
USART 0
USART 0
USART 1
USART 1
Flash controller
Radio (not in CC2540)
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
AES
AES
Debug interface
Table 8-2. DMA Configuration-Data Structure
Name
DMA channel source address, high
DMA channel source address, low
DMA channel destination address, high. Note that flash memory is not directly writable.
DMA channel destination address, low. Note that flash memory is not directly writable.
Variable-length transfer mode. In word mode, bits 12:0 of the first word are considered as
the transfer length.
000: Use LEN for transfer count
001: Transfer the number of bytes or words specified by the first byte or word + 1 (up to
a maximum specified by LEN). Thus, the transfer count excludes the length byte or
word.
010: Transfer the number of bytes or words specified by the first byte or word (up to a
maximum specified by LEN). Thus, the transfer count includes the length byte or
word.
011: Transfer the number of bytes/words specified by the first byte/word + 2 (up to a
maximum specified by LEN).
100: Transfer the number of bytes/words specified by the first byte/word + 3 (up to a
maximum specified by LEN).
101: Reserved
110: Reserved
111: Alternative for using LEN as the transfer count
The DMA channel transfer count
Copyright © 2009–2014, Texas Instruments Incorporated
Description
(1)
Port 0 I/O pin input transition
(1)
Port 1 I/O pin input transition
USART 0 RX complete
USART 0 TX complete
USART 1 RX complete
USART 1 TX complete
Flash data write complete
CC253x: RF packet byte received (see
CC2541: Radio DMA trigger 0 (see
ADC end of a conversion in a sequence, sample ready
ADC end of conversion channel 0 in sequence, sample ready
ADC end of conversion channel 1 in sequence, sample ready
ADC end of conversion channel 2 in sequence, sample ready
ADC end of conversion channel 3 in sequence, sample ready
ADC end of conversion channel 4 in sequence, sample ready
ADC end of conversion channel 5 in sequence, sample ready
ADC end of conversion channel 6 in sequence, sample ready
ADC end of conversion channel 7 in sequence, sample ready
AES encryption processor requests download of input data
AES encryption processor requests upload of output data
Debug interface burst write
Description
DMA Memory Access
Section 23.3)
Section 25.3.2)
DMA Controller
99