Sfr Overview - Texas Instruments CC253x User Manual

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Register
Name
ADCCON1
ADCCON2
ADCCON3
ADCL
ADCH
RNDL
RNDH
ENCDI
ENCDO
ENCCS
P0
SP
DPL0
DPH0
DPL1
DPH1
PCON
TCON
P1
DPS
S0CON
IEN2
S1CON
P2
IEN0
IP0
IEN1
IP1
IRCON
PSW
ACC
IRCON2
B
DMAIRQ
DMA1CFGL
DMA1CFGH
DMA0CFGL
DMA0CFGH
DMAARM
DMAREQ
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P0IFG
SWRU191F – April 2009 – Revised April 2014
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Table 2-1. SFR Overview
SFR
Module
Address
0xB4 ADC ADC control 1
0xB5 ADC ADC control 2
0xB6 ADC ADC control 3
0xBA ADC ADC data low
0xBB ADC ADC data high
0xBC ADC Random number generator data low
0xBD ADC Random number generator data high
0xB1 AES Encryption or decryption input data
0xB2 AES Encryption or decryption output data
0xB3 AES Encryption or decryption control and status
0x80 CPU Port 0. Readable from XDATA (0x7080)
0x81 CPU Stack pointer
0x82 CPU Data pointer 0 low byte
0x83 CPU Data pointer 0 high byte
0x84 CPU Data pointer 1 low byte
0x85 CPU Data pointer 0 high byte
0x87 CPU Power mode control
0x88 CPU Interrupt flags
0x90 CPU Port 1. Readable from XDATA (0x7090)
0x92 CPU Data pointer select
0x98 CPU Interrupt flags 2
0x9A CPU Interrupt enable 2
0x9B CPU Interrupt flags 3
0xA0 CPU Port 2. Readable from XDATA (0x70A0)
0xA8 CPU Interrupt enable 0
0xA9 CPU Interrupt priority 0
0xB8 CPU Interrupt enable 1
0xB9 CPU Interrupt priority 1
0xC0 CPU Interrupt flags 4
0xD0 CPU Program status Word
0xE0 CPU Accumulator
0xE8 CPU Interrupt flags 5
0xF0 CPU B register
0xD1 DMA DMA interrupt flag
0xD2 DMA DMA channel 1–4 configuration address low
0xD3 DMA DMA channel 1–4 configuration address high
0xD4 DMA DMA channel 0 configuration address low
0xD5 DMA DMA channel 0 configuration address high
0xD6 DMA DMA channel armed
0xD7 DMA DMA channel start request and status
0xAA — Reserved
0x8E — Reserved
0x99 — Reserved
0xB0 — Reserved
0xB7 — Reserved
0xC8 — Reserved
0x89 IOC Port 0 interrupt status flag
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Description
Memory
29
8051 CPU