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11.1 General
The Sleep Timer is a 24-bit timer running on the 32-kHz clock (either RCOSC or XOSC). The timer starts
running immediately after a reset and continues to run uninterrupted.
The current value of the timer can be read from SFR registers ST2:ST1:ST0. When ST0 is read, the
current value of the 24-bit counter is latched. Thus, the ST0 register must be read before ST1 and ST2 to
read a correct Sleep Timer count value.
The Sleep Timer is running when operating in all power modes except PM3. The value of the Sleep Timer
is not preserved in PM3. When returning from PM1 or PM2 (where the system clock is shut down), the
Sleep Timer value in ST2:ST1:ST0 is not up-to-date until a positive edge on the 32-kHz clock has been
detected after the system clock restarted. To ensure an updated value is read, wait for a positive transition
on the 32-kHz clock by polling the SLEEPSTA.CLK32K bit, before reading the Sleep Timer value.
Note that if supply voltage drops below 2 V while in PM2, the sleep interval might be affected.
11.2 Timer Compare
A timer compare event occurs when the timer value is equal to the 24-bit compare value and there is a
positive edge on the 32-kHz clock. The compare value is set by writing to registers ST2:ST1:ST0. Writing
to ST0 while STLOAD.LDRDY is 1 initiates loading of the new compare value, that is, the most-recent
values written to the ST2, ST1, and ST0 registers. This means that when writing a compare value, ST2
and ST1 must be written before ST0. STLOAD.LDRDY is 0 during the load, and software must not start a
new load until STLOAD.LDRDY has flipped back to 1.
When setting a new compare value, the value should be at least 5 more than the current sleep timer
value. Otherwise, the timer compare event may be lost.
The interrupt enable bit for the ST interrupt is IEN0.STIE, and the interrupt flag is IRCON.STIF. When a
timer compare event occurs, the interrupt flag IRCON.STIF is asserted.
In PM1 and PM2, the Sleep Timer compare event may be used to wake up the device and return to active
operation in active mode. The default value of the compare value after reset is 0xFF FFFF.
For all devices except the CC2540 and CC2541, the Sleep Timer compare event can also be used as a
DMA trigger (DMA trigger 11 in
Note that if supply voltage drops below 2 V while in PM2, the sleep interval might be affected.
11.3 Timer Capture
The timer capture occurs when the interrupt flag for a selected I/O pin is set and this event has been
dectected by the 32-kHz clock. Sleep Timer capture is enabled by setting STCC.PORT[1:0] and
STCC.PIN[2:0] to the I/O pin that is to be used to trigger the capture. When STCS.VALID goes high,
the capture value in STCV2:STCV1:STCV0 can be read. The captured value is 1 more than the value at
the instant for the event on the I/O pin. Software should therefore subtract 1 from the captured value if
absolute timing is required. To enable a new capture, follow these steps:
1. Clear STCS.VALID.
2. Wait until SLEEPSTA.CLK32K is low.
3. Wait until SLEEPSTA.CLK32K is high.
4. Clear the pin interrupt flag in the P0IFG,
P1IFG, or P2IFG register.
This sequence, using the rising edge on P0.0 as an example, is shown in
procedure may cause the capture functionality to stop working until a chip reset.
SWRU191F – April 2009 – Revised April 2014
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Table
8-1).
Copyright © 2009–2014, Texas Instruments Incorporated
Figure
11-1. Failure to follow the
Sleep Timer
General
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