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Periphery/
Function
7
ADC
A7
A6
Operational
amplifier
Analog
comparator
USART 0 SPI
Alt. 2
USART 0
UART
Alt. 2
USART 1 SPI
Alt. 2
USART 1
UART
Alt. 2
TIMER 1
Alt. 2
3
TIMER 3
Alt. 2
TIMER 4
Alt. 2
32-kHz XOSC
DEBUG
OBSSEL
7.6.1 Timer 1
PERCFG.T1CFG selects whether to use alternative 1 or alternative 2 locations.
In
Table
7-1, the Timer 1 signals are shown as the following:
•
0: Channel 0 capture or compare pin
•
1: Channel 1 capture or compare pin
•
2: Channel 2 capture or compare pin
•
3: Channel 3 capture or compare pin
•
4: Channel 4 capture or compare pin
P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to Port 0. When set to
10, Timer 1 channels 0–1 have precedence, and when set to 11, Timer 1 channels 2–3 have precedence.
To have all Timer 1 channels visible in the alternative 1 location, move both USART 0 and USART 1 to
the alternative 2 location.
P2SEL.PRI1P1 and P2SEL.PRI0P1 select the order of precedence when assigning several peripherals
to Port 1. The Timer 1 channels have precedence when the former is set low and the latter is set high.
7.6.2 Timer 3
PERCFG.T3CFG selects whether to use alternative 1 or alternative 2 locations.
In
Table
7-1, the Timer 3 signals are shown as the following:
•
0: Channel 0 capture or compare pin
•
1: Channel 1 capture or compare pin
SWRU191F – April 2009 – Revised April 2014
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Table 7-1. Peripheral I/O Pin Mapping
P0
6
5
4
3
2
1
A5
A4
A3
A2
A1
O
–
+
–
C
SS
MO
MI
RT
CT
TX
RX
MI
M0
C
SS
RX
TX
RT
CT
4
3
2
1
0
4
Copyright © 2009–2014, Texas Instruments Incorporated
P1
0
7
6
5
4
3
A0
+
M0
MI
C
TX
RX
RT
MI
M0
C
SS
RX
TX
RT
CT
1
0
1
0
5
4
3
Peripheral I/O
P2
2
1
0
4
3
2
SS
CT
0
1
2
1
0
1
Q1
Q2
DC
2
1
0
I/O Ports
1
0
T
0
DD
81
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