Register Settings Update; Registers That Should Be Updated From Their Default Value, Bit Rates 1 Mbps And Lower; Registers That Should Be Updated From Their Default Value, Bit Rate 2 Mbps - Texas Instruments CC253x User Manual

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Address (Hex)
BSP_P0
0x61E0
BSP_D0
0x61E4
BSP_W
0x61E8
SW4
0x61F8
DC_I_L
0x61FC

25.12.2 Register Settings Update

This section contains a summary of the register settings that should be updated from their default value to
have optimal performance. For some of the registers, the setting depends on the required gain in the
receiver chain for bit rates of 1 Mbps and lower. For 2 Mbps, other values are needed, and different
values should be used for RX and TX tasks. Note that registers that are listed only in the 2-Mbps table
should have their default values when operating at 1 Mbps and lower, and vice versa.
Table 25-24. Registers That Should Be Updated From Their Default Value,
Register Name
FRMCTRL0
MDMCTRL1
MDMCTRL2
MDMCTRL3
RXCTRL
FSCTRL
LNAGAIN
TXFILTCFG
TXPOWER
TXCTRL
IVCTRL
(1)
Not all modulation types are characterized for the standard gain setting; see the CC2541 2.4-GHz Bluetooth low energy and
Proprietary System-on-Chip data sheet (SWRS110).
Table 25-25. Registers That Should Be Updated From Their Default Value, Bit Rate 2 Mbps
Register Name
FRMCTRL0
MDMCTRL1
MDMCTRL2
MDMCTRL3
RXCTRL
SWRU191F – April 2009 – Revised April 2014
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Table 25-23. XREG Register Overview (continued)
+ 0x0000
BSP_P1
BSP_D1
BSP_MODE
SW5
DC_I_H
Bit Rates 1 Mbps and Lower
Standard Gain:
Address (Hex)
New Value (Hex)
6180 43
6191 48
6192 C0
6193 63
619A 33
619B 55
61A0 3A
61BC 03
6186 E1
6187 19
6265 1B
Address (Hex) RX Tasks
6180 43
6191 48
6192 CC
6193 63
619A 29
Copyright © 2009–2014, Texas Instruments Incorporated
+ 0x001 + 0x002
BSP_P2
BSP_D2
BSP_DATA
SW6
DC_Q_L
High Gain:
(1)
New Value (Hex)
43
48
C0
63
3F
5A
7F
03
E1
19
1B
TX Tasks
Amplitude weight in frequency offset
43 compensation (assuming sync word is
included in CRC and MSB first)
Sync word correlation threshold (32-bit sync
48
word)
Use inverse of preamble for frequency offset
CC estimation (assuming MSB first); set extra
preamble bytes
63 Set RSSI mode to peak detect after sync
29 Receiver currents
Registers
+ 0x003
BSP_P3
BSP_D3
SW7
DC_Q_H
Description
Amplitude weight in frequency offset
compensation (assuming sync word
included in CRC and MSB first)
Sync word correlation threshold (32-bit
sync word)
Use inverse of preamble for frequency
offset estimation (assuming MSB first)
Set RSSI mode to peak detect after
sync
Receiver currents
Prescaler and mixer currents
LNA gain
Sets TX anti-aliasing filter to appropriate
bandwidth
TX power (0 dBm)
DAC current
PA, mixer, and DAC bias
Description
CC2541 Proprietary Mode Radio
321