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23.14.2 Data Registers
The CSP has four data registers, CSPT, CSPX, CSPY, and CSPZ, which are read- and write-accessible for
the CPU as XREG registers. These registers are read or modified by some instructions, thus allowing the
CPU to set parameters to be used by a CSP program, or allowing the CPU to read CSP program status.
The CSPT data register is not modified by any instruction. The CSPT data register is used to set a MAC
Timer overflow-compare value. Once program execution has started on the CSP, the content of this
register is decremented by 1 each time the MAC Timer overflows. When CSPT reaches zero, program
execution is halted and the interrupt IRQ_CSP_STOP is asserted. The CSPT register is not decremented if
the CPU writes 0xFF to this register.
NOTE: If the
CSPT
the program execution is started.
23.14.3 Program Execution
After the instruction memory has been filled, program execution is started by writing the immediate
command strobe instruction ISSTART to the RFST register. Program execution continues until the
instruction at the last location has been executed, the CSPT data register content is zero, an SSTOP
instruction has been executed, an immediate ISSTOP instruction is written to RFST, or a SKIP instruction
returns a location beyond the last location in the instruction memory. The CSP runs at the set system
clock frequency, which must be set to 32 MHz for correct radio operation.
Immediate command strobe instructions may be written to RFST while a program is being executed. In this
case, the immediate instruction is executed before the instruction in the instruction memory, which is
executed once the immediate instruction has been completed.
During program execution, reading RFST returns the current instruction being executed. An exception to
this is the execution of immediate command strobes, during which RFST returns 0xD0.
23.14.4 Interrupt Requests
The CSP has three interrupt flags which can produce the RF interrupt vector. These are the following:
•
IRQ_CSP_STOP: asserted when the processor has executed the last instruction in memory or when
the processor stops due to an SSTOP or ISSTOP instruction or the CSPT register being equal to zero
•
IRQ_CSP_WT: asserted when the processor continues executing the next instruction after a WAIT W
or WAITX instruction
•
IRQ_CSP_INT: asserted when the processor executes an INT instruction
23.14.5 Random Number Instruction
There is a delay in the update of the random number used by the RANDXY instruction. Therefore, if the
instruction RANDXY, which uses this value, is issued immediately after a previous RANDXY instruction,
the random value read may be the same in both cases.
23.14.6 Running CSP Programs
The basic flow for loading and running a program on the CSP is shown in
execution stops at the end of the program, the current program remains in program memory so that the
same program can be run again by starting execution once again with the ISSTART command. To clear
the program contents, use the ISCLEAR instruction.
SWRU191F – April 2009 – Revised April 2014
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register compare function is not used, this register must be set to 0xFF before
Copyright © 2009–2014, Texas Instruments Incorporated
Command Strobe Processor
Figure
23-23. When program
CC253x Radio
239
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