Usb Registers - Texas Instruments CC253x User Manual

USB Registers

21.12 USB Registers
This section describes all USB registers used for control and status for the USB. The USB registers reside
in XDATA memory space in the region 0x6200–0x622B. These registers can be divided into three groups:
The common USB registers, the indexed endpoint registers, and the endpoint FIFO registers. The indexed
endpoint registers represent the currently selected endpoint. The USBINDEX register is used to select the
endpoint.
The registers return to their reset values and the FIFOs are cleared when the chip enters PM2 or PM3.
USBADDR (0x6200) – Function Address
Bit Name Reset
7 UPDATE 0
6:0 USBADDR[6:0] 000 0000 R/W
USBPOW (0x6201) – Power and Control Register
Bit Name Reset
7 ISO_WAIT_SOF 0
6:4 – 000
3 RST 0
2 0
RESUME
1 SUSPEND 0
0 SUSPEND_EN 0
USBIIF (0x6202) – IN Endpoints and EP0 Interrupt Flags
Bit Name Reset
7:6 – 00
5 INEP5IF 0
4 INEP4IF 0
3 INEP3IF 0
2 0
INEP2IF
1 INEP1IF 0
0 EP0IF 0
USBOIF (0x6204) – OUT-Endpoint Interrupt Flags
Bit Name Reset
7:6 – –
5 OUTEP5IF 0
4 0
OUTEP4IF
3 OUTEP3IF 0
2 OUTEP2IF 0
1 OUTEP1IF 0
0 – –
190
USB Controller
R/W Description
This bit is set when the USBADDR register is written and cleared when the address becomes
R
effective.
Device address
R/W Description
R/W When this bit is set to 1, the USB controller sends zero-length data packets from the time
INPKT_RDY is asserted and until the first SOF token has been received. This only applies to
isochronous endpoints.
R0 Reserved
R During reset signaling, this bit is set to 1.
R/W Drives resume signaling for remote wakeup. According to the USB Specification, the duration
of driving resume must be at least 1 ms and no more than 15 ms. It is recommended to keep
this bit set for approximately 10 ms.
Suspend mode entered. This bit is only used when SUSPEND_EN = 1. Reading the USBCIF
R
register or asserting RESUME clears this bit.
R/W Suspend enable. When this bit is set to 1, suspend mode is entered when the USB has been
idle for 3 ms.
R/W Description
R0 Reserved
R, H0 Interrupt flag for IN endpoint 5. Cleared by hardware when read
R, H0 Interrupt flag for IN endpoint 4. Cleared by hardware when read
R, H0 Interrupt flag for IN endpoint 3. Cleared by hardware when read
R, H0 Interrupt flag for IN endpoint 2. Cleared by hardware when read
R, H0 Interrupt flag for IN endpoint 1. Cleared by hardware when read
R, H0 Interrupt flag for endpoint 0. Cleared by hardware when read
R/W Description
R0 Reserved
R, H0 Interrupt flag for OUT endpoint 5. Cleared by hardware when read
R, H0 Interrupt flag for OUT endpoint 4. Cleared by hardware when read
R, H0 Interrupt flag for OUT endpoint 3. Cleared by hardware when read
R, H0 Interrupt flag for OUT endpoint 2. Cleared by hardware when read
R, H0 Interrupt flag for OUT endpoint 1. Cleared by hardware when read
R0 Reserved
Copyright © 2009–2014, Texas Instruments Incorporated
SWRU191F – April 2009 – Revised April 2014
Submit Documentation Feedback
www.ti.com