Texas Instruments CC2533F64 Manuals

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Texas Instruments CC2533F64 User Manual

Texas Instruments CC2533F64 User Manual (355 pages)

system-on-chip for 2.4Ghz

Brand: Texas Instruments | Category: Motherboard | Size: 2.14 MB

Table of Contents

Table of Contents
2
Preface

14
- Cc253X Family Overview
  15
- Register Bit Conventions
  16
Introduction

17
- Overview
  18
- Cc253X Block Diagram
  18
- CC2540 Block Diagram
  19
- CC2541 Block Diagram
  20
  - CPU and Memory
    21
  - Clocks and Power Management
    21
  - Peripherals
    21
  - Radio
    23
  - Applications
    23
8051 Cpu

24
- 8051 CPU Introduction
  25
- Memory
  25
  - Memory Map
    25
- XDATA Memory Space (Showing SFR and DATA Mapping)
  26
- CODE Memory Space
  26
- CODE Memory Space for Running Code from SRAM
  26
  - CPU Memory Space
    27
  - Physical Memory
    28
- SFR Overview
  29
- Overview of XREG Registers
  32
  - XDATA Memory Access
    33
  - Memory Arbiter
    33
  - CPU Registers
    34
    
    Data Pointers
    34
    
    Program Status Word
    35
    
    Registers
    35
    
    Registers R0–R7
    35
    
    Accumulator
    36
    
    B Register
    36
    
    Stack Pointer
    36
  - Instruction Set Summary
    36
- Instruction Set Summary
  37
  - Interrupts
    40
- Instructions that Affect Flag Settings
  40
  - Interrupt Masking
    41
- Interrupts Overview
  41
- Interrupt Overview
  43
  - Interrupt Processing
    45
  - Interrupt Priority
    47
- Priority Level Setting
  48
- Interrupt Priority Groups
  48
- Interrupt Polling Sequence
  49
Debug Interface

50
- Debug Mode
  51
- Debug Communication
  51
- External Debug Interface Timing
  51
- Transmission of One Byte
  51
- Typical Command Sequence-No Extra Wait for Response
  52
  - Debug Commands
    53
- Typical Command Sequence. Wait for Response
  53
  - Debug Configuration
    55
  - Debug Status
    55
- Burst Write Command (First 2 Bytes)
  55
  - Hardware Breakpoints
    56
- Pm_Active
  56
  - Flash Programming
    57
    
    Lock Bits
    57
  - Debug Interface and Power Modes
    57
- Flash Lock-Protection Bit Structure Definition
  57
  - Registers
    59
Power Management and Clocks

60
- Power Management Introduction
  61
- Power Modes
  61
  - Active and Idle Modes
    62
  - Pm1
    62
  - Pm2
    62
  - Pm3
    62
  - Power-Management Control
    62
- Pcon_Idle
  62
  - Power-Management Registers
    63
- Clock System Overview
  65
  - Oscillators and Clocks
    66
    
    Oscillators
    66
    
    System Clock
    66
    
    32-Khz Oscillators
    67
    
    Oscillator and Clock Registers
    67
  - Timer Tick Generation
    69
  - Data Retention
    69
Reset

70
- Power-On Reset and Brownout Detector
  71
- Clock-Loss Detector
  71
Flash Controller

72
- Flash Memory Organization
  73
- Flash Write
  73
  - Flash-Write Procedure
    73
  - Writing Multiple Times to a Word
    74
  - DMA Flash Write
    74
- Example Write Sequence
  74
  - CPU Flash Write
    75
  - Flash
    75
- Flash Write Using DMA
  75
I/O Ports

78
- Unused I/O Pins
  79
- Low I/O Supply Voltage
  79
- General-Purpose I/O
  79
- General-Purpose I/O Interrupts
  79
- General-Purpose I/O DMA
  80
- Peripheral I/O
  80
  - Timer 1
    81
  - Timer 3
    81
- Peripheral I/O Pin Mapping
  81
  - Timer 4
    82
  - Usart 0
    82
  - Usart
    82
  - Adc
    83
  - Operational Amplifier and Analog Comparator
    83
  - Debug Interface
    83
  - 32-Khz XOSC Input
    83
  - Radio Test Output Signals
    84
  - Power-Down Signal MUX (PMUX)
    84
  - I/O Registers
    84
DMA Controller

92
- DMA Operation
  93
- DMA Operation
  94
  - DMA Configuration Parameters
    95
    
    Destination Address
    95
    
    Source Address
    95
    
    Transfer Count
    95
    
    Source and Destination Increment
    96
    
    Trigger Event
    96
    
    VLEN Setting
    96
- Variable Length (VLEN) Transfer Options
  96
  - DMA Transfer Mode
    97
  - DMA Priority
    97
  - Byte or Word Transfers
    97
  - Interrupt Mask
    97
  - Mode 8 Setting
    97
  - DMA Configuration Setup
    97
  - Stopping DMA Transfers
    98
  - DMA Interrupts
    98
  - DMA Configuration-Data Structure
    98
  - DMA Memory Access
    98
- DMA Trigger Sources
  98
- DMA Configuration-Data Structure
  99
  - DMA Registers
    101
Timer 1 (16-Bit Timer)

103
- 16-Bit Counter
  104
- Timer 1 Operation
  104
- Free-Running Mode
  104
- Modulo Mode
  105
- Up-And-Down Mode
  105
- Channel-Mode Control
  105
- Input Capture Mode
  106
- Output Compare Mode
  106
- Initial Compare Output Values (Compare Mode)
  107
- Output Compare Modes, Timer Free-Running Mode
  108
- Output Compare Modes, Timer Modulo Mode
  109
- Output Compare Modes, Timer Up-And-Down Mode
  110
  - IR Signal Generation and Learning
    111
    
    Introduction
    111
    
    Modulated Codes
    111
- Frequency Error Calculation for 38-Khz Carrier
  111
  - Non-Modulated Codes
    112
- Block Diagram of Timers in IR-Generation Mode
  112
- Modulated Waveform Example
  112
  - Learning
    113
  - Other Considerations
    113
  - Timer 1 Interrupts
    113
  - Timer 1 DMA Triggers
    113
- IR Learning Board Diagram
  113
  - Timer 1 Registers
    114
  - Accessing Timer 1 Registers as Array
    119
Timer 3 and Timer 4 (8-Bit Timers)

120
- 8-Bit Timer Counter
  121
- Timer 3 and Timer 4 Mode Control
  121
  - Free-Running Mode
    121
  - Down Mode
    121
  - Modulo Mode
    121
  - Up-And-Down Mode
    121
- Channel Mode Control
  121
- Input Capture Mode
  122
- Output Compare Mode
  122
- Timer 3 and Timer 4 Interrupts
  122
- Initial Compare Output Values (Compare Mode)
  122
  - Timer 3 and Timer 4 DMA Triggers
    123
  - Timer 3 and Timer 4 Registers
    123
Sleep Timer

128
- General
  129
- Timer Compare
  129
- Timer Capture
  129
- Sleep Timer Registers
  130
- Sleep Timer Capture (Example Using Rising Edge on P0_0)
  130
Adc

132
- ADC Introduction
  133
- ADC Operation
  133
  - ADC Inputs
    133
- ADC Block Diagram
  133
  - ADC Conversion Sequences
    134
  - Single ADC Conversion
    134
  - ADC Operating Modes
    134
  - ADC Conversion Results
    135
  - ADC Reference Voltage
    135
  - ADC Conversion Timing
    135
  - ADC Interrupts
    135
  - ADC DMA Triggers
    135
  - ADC Registers
    136
Battery Monitor

139
Random-Number Generator

143
- Introduction
  144
- Random-Number-Generator Operation
  144
  - Pseudorandom Sequence Generation
    144
  - Seeding
    144
  - Crc16
    144
- Basic Structure of the Random-Number Generator
  144
  - Random-Number-Generator Registers
    145
AES Coprocessor

146
- AES Operation
  147
- Key and IV
  147
- Padding of Input Data
  147
- Interface to CPU
  147
- Modes of Operation
  147
- Cbc-Mac
  147
- CCM Mode
  148
- Message Authentication Phase Block B0
  148
- Authentication Flag Byte
  148
- Message Encryption Phase Block
  149
- Encryption Flag Byte
  149
  - AES Interrupts
    150
  - AES DMA Triggers
    150
  - AES Registers
    150
Watchdog Timer

152
- Watchdog Mode
  153
- Timer Mode
  153
- Watchdog Timer Register
  153
Usart

155
- UART Mode
  156
  - UART Transmit
    156
  - UART Receive
    156
  - UART Hardware Flow Control
    156
  - UART Character Format
    157
- SPI Mode
  157
  - SPI Master Operation
    157
  - SPI Slave Operation
    158
- SSN Slave-Select Pin
  158
- Baud-Rate Generation
  158
- Commonly Used Baud-Rate Settings for 32 Mhz System Clock
  158
  - USART Flushing
    159
  - USART Interrupts
    159
  - USART DMA Triggers
    159
  - USART Registers
    159
Operational Amplifier

164
- Description
  165
- Calibration
  165
- Clock Source
  165
- Registers
  165
Analog Comparator

166
- Description
  167
- Register
  167
- Analog Comparator
  167
  - Operation
    169
20 I C

169
- Block Diagram of the I
  169
  - Module
    169
    
    C Initialization and Reset
    170
    
    Serial Data
    170
  - Bus Connection Diagram
    170
  - Module Data Transfer
    170
    
    C Addressing Modes
    171
    
    C Module Operating Modes
    171
- Bit Transfer on I
  171
  - Bus
    171
  - Module 7-Bit Addressing Format
    171
- C Module Addressing Format with Repeated START Condition
  171
- Slave Transmitter Mode
  172
- Slave Receiver Mode
  173
- Master Transmitter Mode
  175
- Master Receiver Mode
  176
  - C Clock Generation and Synchronization
    177
- Arbitration Procedure between Two Master Transmitters
  177
  - Clock Generators During Arbitration
    177
    
    Bus Error
    178
    
    Interrupt
    178
    
    Pins
    178
  - C Registers
    178
- Miscellaneous States
  178
- Clock Rates Defined at 32 Mhz
  179
USB Controller

181
- USB Introduction
  182
- USB Enable
  182
- 48-Mhz USB PLL
  182
- USB Controller Block Diagram
  182
  - USB Interrupts
    183
  - Endpoint 0
    183
  - Endpoint-0 Interrupts
    183
- USB Interrupt Flags Interrupt-Enable Mask Registers
  183
  - Error Conditions
    184
  - SETUP Transactions (IDLE State)
    184
  - IN Transactions (TX State)
    184
  - OUT Transactions (RX State)
    185
  - Endpoints
    185
    
    FIFO Management
    185
    
    Double Buffering
    186
- IN and out Fifos
  186
- FIFO Sizes for EP
  186
  - FIFO Access
    187
  - Endpoint 1-5 Interrupts
    187
  - Bulk or Interrupt in Endpoint
    188
  - Isochronous in Endpoint
    188
  - Bulk or Interrupt out Endpoint
    188
  - Isochronous out Endpoint
    188
  - Dma
    189
  - USB Reset
    189
  - Suspend and Resume
    189
  - Remote Wake-Up
    189
  - USB Registers
    190
Timer 2 (MAC Timer)

197
- Timer Operation
  198
  - General
    198
  - Up Counter
    198
  - Timer Overflow
    198
  - Timer Delta Increment
    198
  - Timer Compare
    198
  - Overflow Count
    198
  - Overflow-Count Update
    199
  - Overflow-Count Overflow
    199
  - Overflow-Count Compare
    199
  - Capture Input
    199
  - Long Compare (CC2541 Only)
    199
- Interrupts
  199
- Event Outputs (DMA Trigger and Radio Events)
  200
- Timer Start-And-Stop Synchronization
  200
  - General
    200
  - Timer Synchronous Stop
    200
  - Timer Synchronous Start
    201
- Timer 2 Registers
  202
- Internal Registers
  203
Cc253X Radio

208
- RF Core
  209
  - Interrupts
    209
  - Interrupt Registers
    209
- FIFO Access
  213
- Dma
  213
- Memory Map
  213
  - Rxfifo
    214
  - Txfifo
    214
  - Frame-Filtering and Source-Matching Memory Map
    214
- Frame Filtering and Source Matching Memory Map
  214
  - Frequency and Channel Programming
    215
  - IEEE 802.15.4-2006 Modulation Format
    215
- Modulation
  216
- I/Q Phases When Transmitting a Zero-Symbol Chip Sequence, T
  216
- IEEE 802.15.4-2006 Symbol-To-Chip Mapping
  216
  - IEEE 802.15.4-2006 Frame Format
    217
    
    MAC Layer
    217
    
    PHY Layer
    217
- Schematic View of the IEEE 802.15.4 Frame Format
  217
- Format of the Frame Control Field (FCF)
  217
  - Transmit Mode
    218
    
    TX Control
    218
    
    TX State Timing
    218
    
    TXFIFO Access
    218
    
    Error Conditions
    219
    
    Retransmission
    219
    
    TX Flow Diagram
    219
- Frame Data Written to the TXFIFO
  219
- TX Flow
  220
  - Transmitted Frame Processing
    221
  - Synchronization Header
    221
  - Frame-Length Field
    221
  - Frame Check Sequence
    221
- Single Transmitted Frame
  221
- Transmitted Synchronization Header
  221
  - Interrupts
    222
  - Clear-Channel Assessment
    222
  - Output Power Programming
    222
  - Tips and Tricks
    222
  - Receive Mode
    222
    
    RX Control
    222
- FCS Hardware Implementation
  222
  - RX State Timing
    223
  - Received-Frame Processing
    223
- Single Received Frame and Transmitted Acknowledgment Frame
  223
  - Synchronization Header and Frame-Length Fields
    224
  - Frame Filtering
    224
- SFD Signal Timing
  224
- Filtering Scenarios (Exceptions Generated During Reception)
  226
  - Source Address Matching
    227
- Matching Algorithm for Short and Extended Addresses
  228
- Interrupts Generated by Source Address Matching
  229
  - Frame-Check Sequence
    230
  - Acknowledgement Transmission
    230
- Data in RXFIFO for Different Settings
  230
- Acknowledge Frame Format
  230
- Acknowledgment Timing
  231
- Command Strobe Timing
  231
  - RXFIFO Access
    232
    
    Using the FIFO and FIFOP
    232
    
    Error Conditions
    233
    
    Rssi
    233
- Behavior of FIFO and FIFOP Signals
  233
  - Link Quality Indication
    234
  - Radio-Control State Machine
    234
- Main FSM
  235
  - Random-Number Generation
    236
- FFT of the Random Bytes
  236
- FSM State Mapping
  236
  - Packet Sniffing and Radio Test Output Signals
    237
- Histogram of 20 Million Bytes Generated with the RANDOM Instruction
  237
  - Command Strobe Processor
    238
    
    Instruction Memory
    238
    
    Data Registers
    239
    
    Interrupt Requests
    239
    
    Program Execution
    239
    
    Random Number Instruction
    239
    
    Running CSP Programs
    239
    
    Registers
    240
- Running a CSP Program
  240
  - Instruction Set Summary
    241
- Instruction Set Summary
  242
  - Instruction Set Definition
    243
  - Registers
    255
- Register Overview
  255
  - Register Settings Update
    256
  - Register Access Modes
    256
- Example Hardware Structure for the R* Register Access Mode
  256
- Registers that Require Update from Their Default Value
  256
- Register-Bit Access Modes
  256
  - Register Descriptions
    257
CC2540 and CC2541 Bluetooth Low Energy Radio

275
- Registers
  276
CC2541 Proprietary Mode Radio

278
- RF Core
  279
- Interrupts
  279
  - Interrupt Registers
    279
- RF Core Data Memory
  280
- Radio RAM
  280
  - Fifos
    281
- Mapping of Radio Memory to MCU XDATA Memory Space
  281
- FIFO Pointers
  281
- Commands to FIFO Via RFST Register
  283
- Access to FIFO Registers
  283
  - Dma
    284
  - RAM-Based Registers
    285
- Address Structure for Auto Mode
  289
- Address Structure for Basic Mode
  290
  - Variables in RAM
    291
  - Bit-Stream Processor
    291
    
    Whitening
    291
- RAM-Based Registers in RAM
  291
  - CC2500-Compatible PN9 Whitening
    292
- PN7 Whitening
  292
  - Crc
    293
- CC2500-Compatible Whitening
  293
- CRC Module
  294
- Register Settings for Different Crcs
  294
  - Coprocessor Mode
    295
- Register Settings for some Commonly Used Crcs, Assuming Initialization with All 1S
  295
  - Frequency and Channel Programming
    296
  - Modulation Formats
    296
  - Receiver
    296
- Supported Modulation Formats, Data Rates, and Deviations
  296
  - Packet Format
    297
- Air Interface Packet Format for Basic Mode
  297
- Air Interface Packet Format for Auto Mode
  298
- Bits of 9-Bit Header
  298
- Bits of 10-Bit Header
  298
  - RX FIFO Packet Organization
    299
- Structure of Packets in the RX FIFO
  299
  - TX FIFO Packet Organization
    300
  - TX Buffers for ACK Payload
    300
- Structure of Packets in the TX FIFO
  300
- Segments for Holding ACK Payload for each Address Entry
  300
  - Link Layer Engine
    301
    
    Command Register
    302
    
    Radio Tasks
    302
- Commands from MCU to LL Engine Via RFST Register
  302
- Timer 2 Capture Settings
  304
- End-Of-Task Causes
  304
- Recommended RAM Register Settings for Start Tone
  306
- Interrupt and Counter Operation for Received Messages
  307
- Interrupt and Counter Operation for Received Messages
  308
- End-Of-Receive Tasks
  310
- Interrupt and Counter Operation for Received ACK Packets
  312
- End-Of-Transmit Tasks
  313
- Additional Reasons for End-Of-Transmit on Clear-Channel Tasks
  315
- Timing of Packets in RX Tasks
  316
  - RF Test Commands
    317
- Timing of Packets in TX Tasks
  317
  - Random Number Generation
    318
  - Packet Sniffing
    319
- Complete Appended Packet
  319
- Packet-Sniffer Modes of Operation
  319
  - Registers
    320
    
    Register Overview
    320
- XREG Register Overview
  320
  - Register Settings Update
    321
- Registers that Should be Updated from Their Default Value, Bit Rates 1 Mbps and Lower
  321
- Registers that Should be Updated from Their Default Value, Bit Rate 2 Mbps
  321
  - SFR Register Descriptions
    322
Voltage Regulator

342
Available Software

343
A Abbreviations

347
B Additional Information

350
C References

352
Revision History

353
- Important Notice
  354

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