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UART Mode
17.1 UART Mode
For asynchronous serial interfaces, the UART mode is provided. In the UART mode, the interface uses a
two-wire or four-wire interface consisting of the pins RXD and TXD, and optionally RTS and CTS. The
UART mode of operation includes the following features:
•
8 or 9 payload bits
•
Odd, even, or no parity
•
Configurable start- and stop-bit levels
•
Configurable LSB- or MSB-first transfer
•
Independent receive and transmit interrupts
•
Independent receive and transmit DMA triggers
•
Parity and framing error status
The UART mode provides full-duplex asynchronous transfers, and the synchronization of bits in the
receiver does not interfere with the transmit function. A UART byte transfer consists of a start bit, eight
data bits, an optional ninth data or parity bit, and one or two stop bits. Note that the data transferred is
referred to as a byte, although the data can actually consist of eight or nine bits.
The UART operation is controlled by the USART control and status registers, UxCSR, and the UART
control registers, UxUCR, where x is the USART number, 0 or 1.
The UART mode is selected when UxCSR.MODE is set to 1.
17.1.1 UART Transmit
A UART transmission is initiated when the USART receive- and transmit-data buffers, UxDBUF, are
written. The byte is transmitted on the TXDx output pins. The UxDBUF registers are double-buffered.
The UxCSR.ACTIVE bit goes high when the byte transmission starts and low when it ends. When the
transmission ends, the UxCSR.TX_BYTE bit is set to 1. An interrupt request is generated when the
UxDBUF register is ready to accept new transmit data. This happens immediately after the transmission
has been started; hence, a new data byte value can be loaded into the data buffer while the byte is being
transmitted.
17.1.2 UART Receive
Data reception on the UART is initiated when a 1 is written to the UxCSR.RE bit. The UART then searches
for a valid start bit on the RXDx input pin and sets the UxCSR.ACTIVE bit high. When a valid start bit has
been detected, the received byte is shifted into the receive register. The UxCSR.RX_BYTE bit is set and a
receive interrupt is generated when the operation has completed. At the same time, UxCSR.ACTIVE goes
low.
The received data byte is available through the UxDBUF register. When UxDBUF is read, UxCSR.RX_BYTE
is cleared by hardware.
NOTE:
When the application has read
UxCSR.RX_BYTE
UART RX shift register is empty, even though it might hold pending data (typically due to
back-to-back transmission). Consequently, the UART asserts (TTL low) the RT/RTS line,
which allows flow into the UART, leading to potential overflow. Hence, the
UxCSR.RX_BYTE
therefore be controlled solely by the SoC UART itself. Otherwise, the application could
typically experience that the RT/RTS line remains asserted (TTL low), even though a back-
to-back transmission clearly suggests it ought to intermittently pause the flow.
17.1.3 UART Hardware Flow Control
Hardware flow control is enabled when the UxUCR.FLOW bit is set to 1. The RTS output is driven low when
the receive register is empty and reception is enabled. Transmission of a byte does not occur before the
CTS input goes low.
156
USART
, it is important that it does not clear
UxDBUF
. Clearing
UxCSR.RX_BYTE
flag integrates closely with the automatic RT/RTS function and must
Copyright © 2009–2014, Texas Instruments Incorporated
implicitly makes the UART believe that the
SWRU191F – April 2009 – Revised April 2014
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