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6.1
Flash Memory Organization
The flash memory is divided into 2048-byte or 1024-byte flash pages. A flash page is the smallest
erasable unit in the memory, whereas a 32-bit word is the smallest writable unit that can be written to the
flash.
When performing write operations, the flash memory is word-addressable using a 16-bit address written to
the address registers FADDRH:FADDRL.
When performing page-erase operations, the flash memory page to be erased is addressed through the
register bits FADDRH[7:1] (CC2530, CC2531, CC2540, and CC2541) or FADDRH[6:0] (CC2533).
Note the difference in addressing the flash memory; when accessed by the CPU to read code or data, the
flash memory is byte-addressable. When accessed by the flash controller, the flash memory is word-
addressable, where a word consists of 32 bits.
The following sections describe the procedures for flash write and flash page-erase in detail.
6.2
Flash Write
The flash is programmed serially with a sequence of one or more 32-bit words (4 bytes), starting at the
start address (set by FADDRH:FADDRL). In general, a page must be erased before writing can begin. The
page-erase operation sets all bits in the page to 1. The chip-erase command (through the debug interface)
erases all pages in the flash. This is the only way to set bits in the flash to 1. When writing a word to the
flash, the 0-bits are programmed to 0 and the 1-bits are ignored (leaves the bit in the flash unchanged).
Thus, bits are erased to 1 and can be written to 0. It is possible to write multiple times to a word. This is
described in
Section
6.2.1 Flash-Write Procedure
The flash-write sequence algorithm is as follows:
1. Set FADDRH:FADDRL to the start address. (This is the 16 MSBs of the 18-bit byte address).
2. Set FCTL.WRITE to 1. This starts the write-sequence state machine.
3. Write four times to FWDATA within 20 μs (since the last time FCTL.FULL became 0, if not first
iteration). LSB is written first. (FCTL.FULL goes high after the last byte.)
4. Wait until FCTL.FULL goes low. (The flash controller has started programming the 4 bytes written in
step 3 and is ready to buffer the next 4 bytes).
5. Optional status check step:
•
If the 4 bytes were not written fast enough in step 3, the operation has timed out and FCTL.BUSY
(and FCTL.WRITE) are 0 at this stage.
•
If the 4 bytes could not be written to the flash due to the page being locked, FCTL.BUSY (and
FCTL.WRITE) are 0 and FCTL.ABORT is 1.
6. If this was the last 4 bytes then quit, otherwise go to step 3.
The write operation is performed using one of two methods:
•
Using DMA transfer (preferred method)
•
Using CPU, running code from SRAM
The CPU cannot access the flash, for example, to read program code while a flash-write operation is in
progress. Therefore, the program code executing the flash write must be executed from RAM. See
Section 2.2.1
for a description of how to run code from RAM.
When a flash-write operation is executed from RAM, the CPU continues to execute code from the next
instruction after initiation of the flash-write operation (FCTL.WRITE = 1).
Power mode 1, 2, or 3 must not be entered while writing to the flash. Also, the system clock source
(XOSC/RCOSC) must not be changed while writing. Note that setting CLKCONSTA.CLKSPD to a high
value makes it impossible to meet the timing requirement of 20-μs write timing. With CLKCONSTA.CLKSPD
= 111, the clock period is only 4 μs. It is therefore recommended to keep CLKCONSTA.CLKSPD at 000 or
001 while writing to the flash.
SWRU191F – April 2009 – Revised April 2014
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6.2.2.
Copyright © 2009–2014, Texas Instruments Incorporated
Flash Memory Organization
73
Flash Controller
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