Interrupt Masking; Interrupts Overview - Texas Instruments CC253x User Manual

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2.5.1 Interrupt Masking

Each interrupt can be individually enabled or disabled by the interrupt-enable bits in the interrupt-enable
SFRs IEN0, IEN1, and IEN2. The CPU interrupt-enable SFRs are described as follows and summarized
in Table 2-5.
Note that some peripherals have several events that can generate the interrupt request associated with
that peripheral. This applies to Port 0, Port 1, Port 2, Timer 1, Timer 2, Timer 3, Timer 4, DMA controller,
and Radio. These peripherals have interrupt mask bits for each internal interrupt source in the
corresponding SFR or XREG register.
In order to enable any of the interrupts, the following steps must be taken:
1. Clear interrupt flags.
2. Set individual interrupt-enable bit in the peripherals SFR register, if any.
3. Set the corresponding individual interrupt-enable bit in the IEN0, IEN1, or IEN2 register to 1.
4. Enable global interrupt by setting the EA bit in IEN0 to 1.
5. Begin the interrupt service routine at the corresponding vector address of that interrupt. See
for addresses.
Figure 2-4 gives a complete overview of all interrupt sources and associated control and state registers.
Shaded boxes in Figure 2-4
interrupt service routine is called.
shaping. Interrupts missing this are to be treated as level-triggered (apply to ports P0, P1, and P2). The
switch boxes are shown in the default state, and
is, at what time instance the interrupt is generated. As a general rule for pulsed or edge-shaped interrupt
sources, one should clear CPU interrupt flag registers prior to clearing the source flag bit, if available, for
flags that are not automatically cleared. For level sources, one must clear the source prior to clearing the
CPU flag.
Note that when clearing source interrupt flags in a register that contains several flags, interrupts may be
lost if a read-modify-write operation is done (even in a single assembly instruction), as it also clears
interrupt flags that became active between the read and write operation. The source interrupt flags (with
the exception of the USB controller interrupt flags) have the access mode R/W0. This means that writing 1
to a bit has no effect, so 1 should be written to an interrupt flag that is not to be cleared. For instance, to
clear the TIMER2_OVF_PERF bit (bit 3) of T2IRQF in C code, one should do:
T2IRQF = ~(1 <<
and not:
T2IRQF &= ~(1 << 3); //
Interrupt
Number
0 RF core-error situation
1 ADC end of conversion
2 USART 0 RX complete
3 USART 1 RX complete
4 AES encryption or decryption complete
5 Sleep Timer compare
6 Port-2 inputs, USB, or I
7 USART 0 TX complete
8 DMA transfer complete
9 Timer 1 (16-bit) capture, compare, overflow
10 Timer 2
(1)
Hardware-cleared when interrupt service routine is called
(2)
Additional IRQ mask and IRQ flag bits exist.
SWRU191F – April 2009 – Revised April 2014
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are interrupt flags that are automatically cleared by hardware when the
indicates a one-shot, either due to the level source or due to edge
3);
wrong!
Table 2-5. Interrupts Overview
Description
2
C
Copyright © 2009–2014, Texas Instruments Incorporated
or indicates rising- or falling-edge detection, that
Interrupt Interrupt Interrupt Mask,
Name Vector
RFERR 0x03 IEN0.RFERRIE
ADC 0x0B IEN0.ADCIE
URX0 0x13 IEN0.URX0IE
URX1 0x1B IEN0.URX1IE
ENC 0x23 IEN0.ENCIE
ST 0x2B IEN0.STIE
P2INT 0x33
IEN2.P2IE
UTX0 0x3B
IEN2.UTX0IE
DMA 0x43 IEN1.DMAIE
T1 0x4B IEN1.T1IE
T2 0x53 IEN1.T2IE
Interrupts
Table 2-5
Interrupt Flag, CPU
CPU
(1)
TCON.RFERRIF
(1)
TCON.ADCIF
(1)
TCON.URX0IF
(1)
TCON.URX1IF
S0CON.ENCIF
IRCON.STIF
(2)
IRCON2.P2IF
IRCON2.UTX0IF
IRCON.DMAIF
(1) (2)
IRCON.T1IF
(1) (2)
IRCON.T2IF
8051 CPU
41