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The instructions that affect CPU flag settings located in PSW are listed in
on the PSW register or bits in PSW also affect the flag settings. Also note that the cycle count for many
instructions assumes single-cycle access to the memory element being accessed, that is, the best-case
situation. This is not always the case. Reads from flash may take 1–3 cycles, for example.
Mnemonic
ADD A,Rn
ADD A,direct
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
SUBB A,direct
SUBB A,@Ri
SUBB A,#data
INC A
INC Rn
INC direct
INC @Ri
INC DPTR
DEC A
DEC Rn
DEC direct
DEC @Ri
MUL AB
DIV A
DA A
ANL A,Rn
ANL A,direct
ANL A,@Ri
ANL A,#data
ANL direct,A
ANL direct,#data
ORL A,Rn
ORL A,direct
ORL A,@Ri
ORL A,#data
ORL direct,A
ORL direct,#data
XRL A,Rn
XRL A,direct
XRL A,@Ri
XRL A,#data
XRL direct,A
SWRU191F – April 2009 – Revised April 2014
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Table 2-3. Instruction Set Summary
Description
ARITHMETIC OPERATIONS
Add register to accumulator
Add direct byte to accumulator
Add indirect RAM to accumulator
Add immediate data to accumulator
Add register to accumulator with carry flag
Add direct byte to A with carry flag
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment accumulator
Increment register
Increment direct byte
Increment indirect RAM
Increment data pointer
Decrement accumulator
Decrement register
Decrement direct byte
Decrement indirect RAM
Multiply A and B
Divide A by B
Decimal adjust accumulator
LOGICAL OPERATIONS
AND register to accumulator
AND direct byte to accumulator
AND indirect RAM to accumulator
AND immediate data to accumulator
AND accumulator to direct byte
AND immediate data to direct byte
OR register to accumulator
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
OR accumulator to direct byte
OR immediate data to direct byte
Exclusive OR register to accumulator
Exclusive OR direct byte to accumulator
Exclusive OR indirect RAM to accumulator
Exclusive OR immediate data to accumulator
Exclusive OR accumulator to direct byte
Copyright © 2009–2014, Texas Instruments Incorporated
Instruction Set Summary
Table
2-4. Note that operations
Hex Opcode
Bytes
28–2F
1
25
2
26–27
1
24
2
38–3F
1
35
2
36–37
1
34
2
98–9F
1
95
2
96–97
1
94
2
04
1
08–0F
1
05
2
06–07
1
A3
1
14
1
18–1F
1
15
2
16–17
1
A4
1
84
1
D4
1
58–5F
1
55
2
56–57
1
54
2
52
2
53
3
48–4F
1
45
2
46–47
1
44
2
42
2
43
3
68–6F
1
65
2
66–67
1
64
2
62
2
8051 CPU
Cycles
1
2
2
2
1
2
2
2
1
2
2
2
1
2
3
3
1
1
2
3
3
5
5
1
1
2
2
2
3
4
1
2
2
2
3
4
1
2
2
2
3
37
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