Xdata Memory Access; Memory Arbiter - Texas Instruments CC253x User Manual

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XDATA Address
0x62A8
0x62A9
0x62AA
0x62AB
0x62AC
0x62AD
0x62AE
0x62AF
0x62B0
0x62B1
0x62B2
0x62B3
0x62B4
0x62C0
0x62C1
0x62D0

2.2.4 XDATA Memory Access

The MPAGE register is used during instructions MOVX A,@Ri and MOVX @Ri,A. MPAGE gives the 8 most-
significant address bits, whereas the register Ri gives the 8 least-significant bits.
In some 8051 implementations, this type of XDATA access is performed using P2 to give the most-
significant address bits. Existing software may therefore have to be adapted to make use of MPAGE
instead of P2.
MPAGE (0x93) – Memory Page Select
Bit Name
7:0
MPAGE[7:0]

2.2.5 Memory Arbiter

The memory arbiter handles CPU and DMA access to all physical memory except the CPU internal
registers. When an access conflict between the CPU and DMA occurs, the memory arbiter stalls one of
the bus masters so that the conflict is resolved.
The control registers MEMCTR and FMAP are used to control various aspects of the memory subsystem.
The MEMCTR and FMAP registers are described as follows.
MEMCTR.XMAP must be set to enable program execution from RAM.
The flash-bank map register, FMAP, controls mapping of physical 32-KB code banks to the program
address region 0x8000–0xFFFF in CODE memory space.
SWRU191F – April 2009 – Revised April 2014
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Table 2-2. Overview of XREG Registers (continued)
Register Name
Timer 1 channel 1 capture or compare value low (additional
T1CC1L
XREG mapping of SFR register)
Timer 1 channel 1 capture or compare value high (additional
T1CC1H
XREG mapping of SFR register)
Timer 1 channel 2 capture or compare value low (additional
T1CC2L
XREG mapping of SFR register)
Timer 1 channel 2 capture or compare value high (additional
T1CC2H
XREG mapping of SFR register)
T1CC3L Timer 1 channel 3 capture or compare value low
T1CC3H Timer 1 channel 3 capture or compare value high
T1CC4L Timer 1 channel 4 capture or compare value low
T1CC4H Timer 1 channel 4 capture or compare value high
STCC Sleep Timer capture control
STCS Sleep Timer capture status
STCV0 Sleep Timer capture value byte 0
STCV1 Sleep Timer capture value byte 1
STCV2 Sleep Timer capture value byte 2
OPAMPC Operational amplifier control
OPAMPS Operational amplifier status
CMPCTL Analog comparator control and status
Reset R/W
0x00 R/W Memory page, high-order bits of address in MOVX instruction
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Description
Description
Memory
33
8051 CPU