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8.2
DMA Configuration Parameters
Setup and control of the DMA operation is performed by the user software. This section describes the
parameters which must be configured before a DMA channel can be used.
parameters are set up in software and passed to the DMA controller.
The behavior of each of the five DMA channels is configured with the following parameters:
Source address: The first address from which the DMA channel should read data.
Destination address: The first address to which the DMA channel should write the data read from the
source address. The user must ensure that the destination is writable.
Transfer count: The number of transfers to perform before rearming or disarming the DMA channel
and alerting the CPU with an interrupt request. The length can be defined in the configuration or it can
be defined as described next for the VLEN setting.
VLEN setting: The DMA channel is capable of variable-length transfers, using the first byte or word to
set the transfer length. When doing this, various options are available regarding how to count the
number of bytes to transfer.
Priority: The priority of the DMA transfers for the DMA channel with respect to the CPU and other
DMA channels and access ports.
Trigger event: All DMA transfers are initiated by so-called DMA trigger events. This trigger either
starts a DMA block transfer or a single DMA transfer. In addition to the configured trigger, a DMA
channel can always be triggered by setting its designated DMAREQ.DMAREQx flag. The DMA trigger
sources are described in
Source and destination increment: The source and destination addresses can be controlled to
increment or decrement or not change.
Transfer mode: The transfer mode determines whether the transfer should be a single transfer or a
block transfer, or repeated versions of these.
Byte or word transfers: Determines whether each DMA transfer should be 8-bit (byte) or 16-bit
(word).
Interrupt mask: An interrupt request is generated on completion of the DMA transfer. The interrupt
mask bit controls whether the interrupt generation is enabled or disabled.
M8: Decide whether to use seven or eight bits per byte byte for transfer length. This is only applicable
when doing byte transfers.
A detailed description of all configuration parameters is given in
8.2.1 Source Address
The address in XDATA memory where the DMA channel starts to read data. This can be any XDATA
address – in RAM, in the mapped flash bank (see MEMCTR.XBANK), XREG, or XDATA addressed SFR.
8.2.2 Destination Address
The first address to which the DMA channel should write the data read from the source address. The user
must ensure that the destination is writable. This can be any XDATA address – in RAM, XREG, or XDATA
addressed SFR.
8.2.3 Transfer Count
The number of bytes/words that must be transferred for the DMA transfer to be complete. When the
transfer count is reached, the DMA controller rearms or disarms the DMA channel and alerts the CPU with
an interrupt request. The transfer count can be defined in the configuration or it can be defined as
variable-length, as described in
SWRU191F – April 2009 – Revised April 2014
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Table
8-1.
Section
8.2.4.
Copyright © 2009–2014, Texas Instruments Incorporated
DMA Configuration Parameters
Section 8.3
describes how the
Section 8.2.1
through
Section
DMA Controller
8.2.11.
95
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