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Table 17-1. Commonly Used Baud-Rate Settings for 32 MHz System
Baud Rate (bps)
28,800
38,400
57,600
76,800
115,200
230,400
17.5 USART Flushing
The current operation can be aborted by setting the UxUCR.FLUSH register bit. This event stops the
current operation and clears all data buffers. Note that when setting the flush bit during the TX or RX of a
bit, the flushing does not take place until TX or RX of this bit has ended (buffers are cleared immediately,
but timers keeping knowledge of bit duration are not). Thus, using the flush bit should either be aligned
with USART interrupts or use a wait time of one bit duration at the current baud rate before updated data
or configuration can be received by the USART.
17.6 USART Interrupts
Each USART has two interrupts. These are the RX complete interrupt (URXx) and the TX interrupt
(UTXx). The TX interrupt is triggered when transmission starts and the data buffer is offloaded.
The USART interrupt enable bits are found in the IEN0 and IEN2 registers. The interrupt flags are located
in the TCON and IRCON2 registers. See
and flags are summarized as follows.
Interrupt enables:
•
USART0 RX: IEN0.URX0IE
•
USART1 RX: IEN0.URX1IE
•
USART0 TX: IEN2.UTX0IE
•
USART1 TX: IEN2.UTX1IE
Interrupt flags:
•
USART0 RX: TCON.URX0IF
•
USART1 RX: TCON.URX1IF
•
USART0 TX: IRCON2.UTX0IF
•
USART1 TX: IRCON2.UTX1IF
17.7 USART DMA Triggers
There are two DMA triggers associated with each USART. The DMA triggers are activated by RX
complete and TX complete events, that is, the same events as the USART interrupt requests. A DMA
channel can be configured using a USART receive-and-transmit buffer, UxDBUF, as source or destination
address.
See
Table 8-1
for an overview of the DMA triggers.
17.8 USART Registers
The registers for the USART are described in this section. For each USART, there are five registers
consisting of the following (x refers to the USART number, that is, 0 or 1):
•
UxCSR, USART x control and status
•
UxUCR, USART x UART control
SWRU191F – April 2009 – Revised April 2014
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Clock (continued)
UxBAUD.BAUD_M
UxGCR.BAUD_E
216
59
216
59
216
216
Section 2.5
for details of these registers. The interrupt enables
Copyright © 2009–2014, Texas Instruments Incorporated
Error (%)
9
0.03
10
0.14
10
0.03
11
0.14
11
0.03
12
0.03
USART Flushing
159
USART
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