Accessing Timer 1 Registers As Array - Texas Instruments CC253x User Manual

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T1CCTL4 (0x62A4) – Timer 1 Channel 4 Capture or Compare Control
Bit Name Reset R/W
7 RFIRQ 0 R/W
6 1 R/W
IM
5:3 CMP[2:0] 000 R/W
2 MODE 0 R/W
1:0 CAP[1:0] 00 R/W
T1CC4H (0x62AF) – Timer 1 Channel 4 Capture or Compare Value, High
Bit Name Reset
7:0 T1CC4[15:8] 0x00
T1CC4L (0x62AE) – Timer 1 Channel 4 Capture or Compare Value, Low
Bit Name Reset
7:0 T1CC4[7:0] 0x00
IRCTL (0x6281) – Timer 1 IR Generation Control
Bit Name Reset
7:1 – 0000 000 R/W
0 IRGEN 0

9.13 Accessing Timer 1 Registers as Array

The Timer 1 capture or compare channel registers can be accessed as a contiguous region in the XDATA
memory space. This facilitates accessing the registers as a simple indexed structure. The five capture or
compare control registers are mapped to 0x62A0–0x62A4. The 16-bit capture or compare values are
mapped to 0x62A6–0x62AF; 0x62A5 is unused.
SWRU191F – April 2009 – Revised April 2014
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Description
When set, use RF interrupt for capture instead of regular capture input.
Channel 4 interrupt mask. Enables interrupt request when set.
Channel 4 compare mode select. Selects action on output when timer value equals compare value in
T1CC4.
000: Set output on compare
001: Clear output on compare
010: Toggle output on compare
011: Set output on compare-up, clear on compare down in up-and-down mode. Otherwise set output
on compare, clear on 0.
100: Clear output on compare-up, set on compare down in up-and-down mode. Otherwise clear
output on compare, set on 0.
Clear when equal T1CC0, set when equal T1CC4
101:
Set when equal T1CC0, clear when equal T1CC4
110:
Initialize output pin. CMP[2:0] is not changed.
111:
Mode. Select Timer 1 channel 4 capture or compare mode
0: Capture mode
1: Compare mode
Channel 4 capture-mode select
00: No capture
01: Capture on rising edge
10: Capture on falling edge
11: Capture on all edges
R/W Description
R/W Timer 1 channel 4 capture or compare value high-order byte. Writing to this register when
T1CCTL4.MODE = 1 (compare mode) causes the T1CC4[15:0] update to the written value to be
delayed until T1CNT = 0x0000.
R/W Description
R/W Timer 1 channel 4 capture or compare value low-order byte. Data written to this register is stored
in a buffer but not written to T1CC4[7:0] until, and at the same time as, a later write to T1CC4H
takes effect.
R/W Description
Reserved
R/W When this bit is set, a connection between Timer 3 channel 1 and Timer 1 tick input is made so
that the timers can be used to generate modulated IR codes (see also
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Accessing Timer 1 Registers as Array
Section 9.9).
Timer 1 (16-Bit Timer)
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