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10.1 8-Bit Timer Counter
All timer functions are based on the main 8-bit counter found in Timer 3 and Timer 4. The counter
increments or decrements at each active clock edge. The period of the active clock edges, as defined by
the register bits CLKCONCMD.TICKSPD[2:0], is further multiplied (the frequency is divided) by the
prescaler value set by TxCTL.DIV[2:0] (where x refers to the timer number, 3 or 4). The counter
operates as either a free-running counter, a down counter, a modulo counter, or an up-and-down counter.
It is possible to read the 8-bit counter value through the SFR register TxCNT, where x refers to the timer
number, 3 or 4.
The possibility to clear and halt the counter is given with TxCTL control register settings. The counter is
started when a 1 is written to TxCTL.START. If a 0 is written to TxCTL.START, the counter halts at its
present value.
10.2 Timer 3 and Timer 4 Mode Control
In general, the control register TxCTL is used to control the timer operation.
10.2.1 Free-Running Mode
In the free-running mode of operation, the counter starts from 0x00 and increments at each active clock
edge. When the counter reaches 0xFF, the counter is loaded with 0x00 and continues incrementing its
value. When the terminal count value 0xFF is reached (that is, an overflow occurs), the interrupt flag
TIMIF.TxOVFIF is set. An interrupt request is generated if enabled; see
free-running mode can be used to generate independent time intervals and output-signal frequencies.
10.2.2 Down Mode
In the down mode, after the timer has been started, the counter is loaded with the contents in TxCC0. The
counter then counts down to 0x00. The interrupt flag TIMIF.TxOVFIF is set when 0x00 is reached. An
interrupt request is generated if enabled; see
be used in applications where an event time-out interval is required.
10.2.3 Modulo Mode
When the timer operates in modulo mode, the 8-bit counter starts at 0x00 and increments at each active
clock edge. After the count has reached the period value held in register TxCC0, the counter is reset to
0x00 and continues to increment. If the timer started with a value above TxCC0, the interrupt flag
TIMIF.TxOVFIF is set when the terminal value (0xFF) is reached, after which the counter wraps to 0x00.
An interrupt request is generated if enabled; see
at the period value, this can be obtained by enabling an output compare interrupt on channel 0, as
explained in
Section
is required.
10.2.4 Up-and-Down Mode
In the up-and-down timer mode, the counter repeatedly starts from 0x00 and counts up until the value held
in TxCC0 is reached, and then the counter counts down until 0x00 is reached. This timer mode is used
when symmetrical output pulses are required with a period other than 0xFF, allowing implementation of
center-aligned PWM output applications. The interrupt flag TIMIF.TxOVFIF is set when the counter value
reaches 0x00 in the up-and-down mode. An interrupt request is generated if enabled; see
details.
Clearing the counter by writing to TxCTL.CLR also resets the count direction to the count-up-from-0x00
mode.
10.3 Channel Mode Control
The channel modes for each channel, 0 and 1, are set by the control and status registers TxCCTLn,
where n is the channel number, 0 or 1. The settings include capture and compare modes.
SWRU191F – April 2009 – Revised April 2014
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Section 10.6
10.5. The modulo mode can be used for applications where a period other than 0xFF
Copyright © 2009–2014, Texas Instruments Incorporated
Section 10.6
for details. The timer down mode can generally
Section 10.6
for details. If a periodic interrupt is wanted
Timer 3 and Timer 4 (8-Bit Timers)
8-Bit Timer Counter
for details. The
Section 10.6
for
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