Table of Contents
Advertisement
www.ti.com
8.2.7 DMA Transfer Mode
The transfer mode determines how the DMA channel behaves when it starts transferring data. There are
four transfer modes described as follows:
Single: On a trigger, a single DMA transfer occurs, and the DMA channel awaits the next trigger. After
the number of transfers specified by the transfer count is completed, the CPU is notified, and the DMA
channel is disarmed.
Block: On a trigger, the number of DMA transfers specified by the transfer count is performed as
quickly as possible, after which the CPU is notified and the DMA channel is disarmed.
Repeated single: On a trigger, a single DMA transfer occurs, and the DMA channel awaits the next
trigger. After the number of transfers specified by the transfer count is completed, the CPU is notified,
and the DMA channel is rearmed.
Repeated block: On a trigger, the number of DMA transfers specified by the transfer count is
performed as quickly as possible, after which the CPU is notified and the DMA channel is rearmed.
8.2.8 DMA Priority
A DMA priority is configurable for each DMA channel. The DMA priority is used to determine the winner in
the case of multiple simultaneous internal memory requests, and whether the DMA memory access should
have priority or not over a simultaneous CPU memory access. In case of an internal tie, a round-robin
scheme is used to ensure access for all. There are three levels of DMA priority:
High: Highest internal priority. DMA access always prevails over CPU access.
Normal: Second-highest internal priority. DMA access prevails over the CPU on at least every second
try.
Low: Lowest internal priority. DMA access always defers to a CPU access.
8.2.9 Byte or Word Transfers
Determines whether 8-bit (byte) or 16-bit (word) transfers are done.
8.2.10 Interrupt Mask
On completing a DMA transfer, the channel can generate an interrupt to the processor. This bit masks the
interrupt.
8.2.11 Mode 8 Setting
This field determines whether to use 7 or 8 bits per byte for transfer length. Only applicable when doing
byte transfers.
8.3
DMA Configuration Setup
The DMA channel parameters such as address mode, transfer mode, and priority, described in the
previous section, must be configured before a DMA channel can be armed and activated. The parameters
are not configured directly through SFR registers, but instead they are written in a special DMA
configuration-data structure in memory. Each DMA channel in use requires its own DMA configuration-
data structure. The DMA configuration-data structure consists of eight bytes and is described in
Section
8.6. A DMA configuration-data structure may reside at any location decided on by the user
software, and the address location is passed to the DMA controller through a set of SFRs,
DMAxCFGH:DMAxCFGL. Once a channel has been armed, the DMA controller reads the configuration data
structure for that channel, given by the address in DMAxCFGH:DMAxCFGL.
It is important to note that the method for specifying the start address for the DMA configuration data
structure differs between DMA channel 0 and DMA channels 1–4 as follows:
DMA0CFGH:DMA0CFGL gives the start address for the DMA channel 0 configuration data structure.
DMA1CFGH:DMA1CFGL gives the start address for the DMA channel 1 configuration data structure,
followed by the channel 2–4 configuration-data structures.
SWRU191F – April 2009 – Revised April 2014
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
DMA Configuration Parameters
DMA Controller
97
Hide quick links:
Advertisement
Table of Contents
