Dma Registers - Texas Instruments CC253x User Manual

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8.8

DMA Registers

This section describes the SFR registers associated with the DMA controller.
DMAARM (0xD6) – DMA Channel Arm
Bit Name Reset
7 ABORT 0
6:5 – 00
4 0
DMAARM4
3 DMAARM3 0
2 DMAARM2 0
1 0
DMAARM1
0 DMAARM0 0
DMAREQ (0xD7) – DMA Channel Start Request and Status
Bit Name Reset R/W
7:5 – 000 R0
4 DMAREQ4 0 R/W1 H0
3 DMAREQ3 0 R/W1 H0
2 DMAREQ2 0 R/W1 H0
1 DMAREQ1 0 R/W1 H0
0 DMAREQ0 0 R/W1 H0
DMA0CFGH (0xD5) – DMA Channel-0 Configuration Address High Byte
Bit Name Reset
7:0 0x00
DMA0CFG[15:8]
DMA0CFGL (0xD4) – DMA Channel-0 Configuration Address Low Byte
Bit Name Reset
7:0 DMA0CFG[7:0] 0x00
SWRU191F – April 2009 – Revised April 2014
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R/W Description
R0/W DMA abort. This bit is used to stop ongoing DMA transfers. Writing a 1 to this bit aborts all
channels which are selected by setting the corresponding DMAARM bit to 1.
0: Normal operation
1: Abort all selected channels
R/W Reserved
R/W1 DMA arm channel 4
This bit must be set in order for any DMA transfers to occur on the channel. For nonrepetitive
transfer modes, the bit is automatically cleared on completion.
R/W1 DMA arm channel 3
This bit must be set in order for any DMA transfers to occur on the channel. For nonrepetitive
transfer modes, the bit is automatically cleared on completion.
R/W1 DMA arm channel 2
This bit must be set in order for any DMA transfers to occur on the channel. For nonrepetitive
transfer modes, the bit is automatically cleared on completion.
R/W1 DMA arm channel 1
This bit must be set in order for any DMA transfers to occur on the channel. For nonrepetitive
transfer modes, the bit is automatically cleared on completion.
R/W1 DMA arm channel 0
This bit must be set in order for any DMA transfers to occur on the channel. For nonrepetitive
transfer modes, the bit is automatically cleared on completion.
Description
Reserved
DMA transfer request, channel 4
When set to 1, activate the DMA channel (has the same effect as a single trigger event). This bit
is cleared when DMA transfer is started.
DMA transfer request, channel 3
When set to 1, activate the DMA channel (has the same effect as a single trigger event). This bit
is cleared when DMA transfer is started.
DMA transfer request, channel 2
When set to 1, activate the DMA channel (has the same effect as a single trigger event). This bit
is cleared when DMA transfer is started.
DMA transfer request, channel 1
When set to 1, activate the DMA channel (has the same effect as a single trigger event). This bit
is cleared when DMA transfer is started.
DMA transfer request, channel 0
When set to 1, activate the DMA channel (has the same effect as a single trigger event). This bit
is cleared when DMA transfer is started.
R/W Description
R/W The DMA channel-0 configuration address, high-order
R/W Description
R/W The DMA channel 0 configuration address, low-order
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DMA Registers
101
DMA Controller