Interrupts; Instructions That Affect Flag Settings - Texas Instruments CC253x User Manual

Interrupts

2.5 Interrupts
The CPU has 18 interrupt sources. Each source has its own request flag located in a set of interrupt-flag
SFR registers. Each interrupt requested by the corresponding flag can be individually enabled or disabled.
The definitions of the interrupt sources and the interrupt vectors are given in
The interrupts are grouped into a set of priority-level groups with selectable priority levels.
The interrupt-enable registers are described in
described in Section
40
8051 CPU
Table 2-4. Instructions That Affect Flag Settings
Instruction
ADD
ADDC
SUBB
MUL
DIV
DA
RRC
RLC
SETB C
CLR C
CPLC
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
CJNE
(1)
0 = set to 0, 1 = set to 1, x = set to 0 or 1, – = not affected
2.5.3.
Copyright © 2009–2014, Texas Instruments Incorporated
CY OV
x x
x x
x x
0 x
0 x
x –
x –
x –
1 –
x –
x –
x –
x –
x –
x –
x –
x –
Section 2.5.1 and the interrupt priority settings are
SWRU191F – April 2009 – Revised April 2014
www.ti.com
(1)
AC
x
x
x
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Table 2-5.
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