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Registers
To set up the packet-sniffer signals or some of the other RF core observation outputs (in total maximum 3;
rfc_obs_sig0, rfc_obs_sig1, and rfc_obs_sig2), the user must perform the following steps:
Step1: Determine which signal (RFC_OBS_CTRL[0–2]) to output on which GPIO pin (P1[0:5]). This is
done using the OBSSELx control registers (OBSSEL0–OBSSEL5) that control the observation output to the
pins P1[0:5] (overriding the standard GPIO behavior for those pins).
Step2: Set the (RFC_OBS_CTRL[0–2]) control registers to select the correct signals (rfc_obs_sig); for
example, for packet sniffing one needs the rfc_sniff_data for the packet-sniffer data signal.and rfc_sniff_clk
for the corresponding clock signal.
Step3: Enable the packet-sniffer module in the MDMCTRL3 register.
25.12 Registers
25.12.1 Register Overview
25.12.1.1 SFR Registers
1 - RFIRQF0 (0xE9) RF interrupt flags
2 - RFIRQF1 (0x91) RF interrupt flags
3 - RFERRF (0xBF) RF error interrupt flags
4 - RFD (0xD9) RF data
5 - RFST (0x6189) LLE and FIFO commands
25.12.1.2 XREG Registers
Address (Hex)
FRMCTRL0
0x6180
FREQCTRL
0x6184
LLESTAT
0x6188
SEMAPHORE2
0x618C
MDMCTRL0
0x6190
SW_CONF
0x6194
SW3
0x6198
0x619C
LNAGAIN
0x61A0
0x61A4
0x61A8
0x61AC
0x61B0
RFC_OBS_CTRL2
0x61BC
TXFILTCFG
0x61C0
RFRAMCFG
RFFDMA1
0x61C4
RFRXFLEN
0x61C8
RFRXFWP
0x61CC
RFTXFLEN
0x61D0
RFTXFWP
0x61D4
320 CC2541 Proprietary Mode Radio
Table 25-23. XREG Register Overview
+ 0x0000
+ 0x001
RFIRQM0
FREQTUNE
RFSTAT
MDMCTRL1
SW0
FREQEST
AAFGAIN
MDMTEST0
ATEST
LLECTRL
RFFSTATUS
RFRXFTHRS
RFRXFRP
RFTXFTHRS
RFTXFRP
Copyright © 2009–2014, Texas Instruments Incorporated
+ 0x002
RFIRQM1
RFERRM
TXPOWER
TXCTRL
SEMAPHORE0
SEMAPHORE1
RSSI
RFPSRND
MDMCTRL2
MDMCTRL3
SW1
SW2
RXCTRL
FSCTRL
ADCTEST0
MDMTEST1
RFC_OBS_CTRL0
RFC_OBS_CTRL1
RFRND
RFFDMA0
RFFCFG
RFRXFWR
RFRXFRD
RFRXFSWP
RFRXFSRP
RFTXFWR
RFTXFRD
RFTXFSWP
RFTXFSRP
SWRU191F – April 2009 – Revised April 2014
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