Table of Contents
Advertisement
www.ti.com
20.1.4.2 Master Mode
2
The I
C module is configured as an I
the master is part of a multi-master system, its own address must be programmed into the
I2CADDR.ADDR register. The value of the I2CADDR.GC bit determines whether the I
to a general call.
2
20.1.4.2.1 I
C Master Transmitter Mode
To enable master transmit mode, set the I2CCFG.ENS1 and I2CCFG.STA bits. The I
2
waits until the I
C bus is free. When the I
address, and transfers a transmit direction bit. It then generates an interrupt, and the first byte of data can
be written to the I2CDATA register. The I
generates another interrupt. The I2CSTAT register contains a value of 0x18 or 0x20, depending on the
received ACK bit (see
either a repeated START condition or a STOP condition. Setting I2CCFG.STA during transmission causes
a repeated START condition to be transmitted. Setting I2CCFG.STO during transmission causes a STOP
condition to be transmitted and the I2CCFG.STO bit to be reset.
Table 20-3
provides more details regarding the master transmitter operation.
Status
Code
Status of the
2
(Value of
I
C
I2CSTAT)
0x08
A START
condition has
been
transmitted.
0x10
A repeated
START
condition has
been
transmitted.
0x18
SLA+W has
been
transmitted;
ACK has been
received.
0x20
SLA+W has
been
transmitted;
not-ACK has
been received.
0x28
Data byte is
transmitted;
ACK is
received.
SWRU191F – April 2009 – Revised April 2014
Submit Documentation Feedback
2
C master by setting the I2CCFG.ENS1 and I2CCFG.STA bits. When
2
C bus is free, it generates a START condition, sends the slave
2
C core sends I2CDATA content if arbitration is not lost, and then
Table
20-3). If a not-ACK is received from the slave, the master must react with
Table 20-3. Master Transmitter Mode
Application Software Response
To or From
I2CDATA
STA
Load SLA+W
X
Load SLA+W
X
or
X
load SLA+R
Load data byte
0
or
1
no action
or
0
no action
or
1
no action
Load data byte
0
or
1
no action
or
0
no action
or
1
no action
Load data byte
0
or
1
no action
or
0
no action
or
1
no action
Copyright © 2009–2014, Texas Instruments Incorporated
To I2CCFG
Next Action Taken by I
STO
SI
AA
0
0
X
SLA+W is transmitted.
ACK is received.
0
0
X
Same as for START condition (0x08)
0
0
X
SLA+W is transmitted; I
mode.
0
0
X
Data byte is transmitted; ACK is received.
0
0
X
Repeated START is transmitted.
1
0
X
STOP condition is transmitted; STO flag is reset.
1
0
X
STOP condition followed by a START condition is
transmitted; STO flag is reset.
0
0
X
Data byte is transmitted; ACK is received.
0
0
X
Repeated START is transmitted.
1
0
X
STOP condition is transmitted; STO flag is reset.
1
0
X
STOP condition followed by a START condition is
transmitted; STO flag is reset.
0
0
X
Data byte is transmitted; ACK is received.
0
0
X
Repeated START is transmitted.
1
0
X
STOP condition is transmitted; STO flag is reset.
1
0
X
STOP condition followed by a START condition is
transmitted; STO flag is reset.
Operation
2
C module responds
2
C module then
2
C Hardware
2
C is switched to MST/REC
175
2
I
C
Hide quick links:
Advertisement
Table of Contents
