Debug Commands; Typical Command Sequence. Wait For Response - Texas Instruments CC253x User Manual

www.ti.com
Time
Debug
Clock
Debug
Cmd Byte
Data
Data Pad
Input
Direction
Figure 3-4. Typical Command Sequence. Wait for Response
If the debug interface indicates by pulling the data line high that it is not ready to return data, the external
device must issue exactly eight clock pulses before it samples the ready level again. This must be
repeated until the level is low. The wait cycle is equivalent to reading a byte from the debug interface, but
ignoring the result. Note that the pad starts to change direction on the falling edge of the debug clock.
Thus, the pad driver drives against the driver in the programmer until the programmer changes pad
direction. This duration should be minimized in a programmer implementation.
3.3

Debug Commands

The debug commands are shown in
detail in the following subsections.
The 3 least-significant bits (the Xs) are don't care values.
Command
CHIP_ERASE 0001 0XXX
WR_CONFIG 0001 1XXX
RD_CONFIG 0010 0XXX
SWRU191F – April 2009 – Revised April 2014
Submit Documentation Feedback
Start of
Command
Sequence
Start to
Change
Direction
Data Byte 1
Table 3-1. Some of the debug commands are described in further
Table 3-1. Debug Commands
Additi Output
Instruction onal Bytes
Byte Input
Bytes
0 1
1 1
0 1
Copyright © 2009–2014, Texas Instruments Incorporated
Pad Is Output, But
Chip Is Not Ready to
Respond
8 Cycles
Data Byte 2
t
dir_change
The Level Is Sampled.
Result = Not Ready
Perform flash chip erase (mass erase) and clear lock bits. If any other
command except READ_STATUS is issued, then the use of CHIP_ERASE
is disabled.
Input byte: none
Output byte: Debug status byte. See
Write debug configuration data.
Input byte: See Table 3-2 for details.
Output byte: Debug status byte. See
Read debug configuration data.
Input byte: none.
Output byte: Returns value set by WR_CONFIG command. See

Debug Commands

End of
Command
Sequence
Output Byte
Output
t
sample_wait
The Level Is Sampled.
Result = Ready
Chip Is Ready to
Provide Response
Description
Table 3-3.
Table 3-3.
Debug Interface
Input
T0305-01
Table 3-2.
53