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Bit-Stream Processor
CRC
p
0
1
0
x
x
d
0
A 32-bit CRC polynomial can be described by the equation x
or 1. To represent this, each P[n] bit in the BSP_P0–BSP_P3 registers should be set to a
should be set to 1. To reduce the size of the polynomial to k, set the bits P[33 – k:0] to 0 and
P[32 – k] to 1. In this case, the initialization value must have zeros at D[33 – k:0]. In practice, only
polynomials of order 8, 16, 24, and 32 are supported, as the number of CRC bits produced in the
transmitter and checked in the receiver is always a multiple of 8. The number of CRC bytes produced in
normal transmit tasks is given by RAM register PRF_CRC_LEN.
This is summarized in
the numbers are binary, with the most significant bit at the left. In the PRF_CRC_INIT column, an X
indicates the initialization value to use (each X does not have to be the same). Some examples are shown
in
Table
25-9.
Order
PRF_CRC_LE
N
8
1
16
2
24
3
32
4
294 CC2541 Proprietary Mode Radio
p
p
2
1
2
x
d
d
1
2
Figure 25-5. CRC Module
Table 25-8
for the four CRC polynomial orders supported. In the BSP_Px column,
Table 25-8. Register Settings for Different CRCs
Polynomial
8
7
1
x
+ a
x
+ ... + a
x
+ 1
7
1
16
15
1
x
+ a
x
+ ... + a
x
+ 1
15
1
24
23
1
x
+ a
x
+ ... + a
x
+ 1
23
1
32
31
1
x
+ a
x
+ ... + a
x
+ 1
31
1
Copyright © 2009–2014, Texas Instruments Incorporated
p
30
30
x
x
d
30
32
31
+ a
x
+ ... + a
31
BSP_Px
BSP_P0
= 0000 0000
BSP_P1
= 0000 0000
BSP_P2
= 0000 0000
BSP_P3
= a
a
a
a
a
a
a
1
7
6
5
4
3
2
1
BSP_P0
= 0000 0000
BSP_P1
= 0000 0000
BSP_P2
= a
a
a
a
a
a
a
1
7
6
5
4
3
2
1
BSP_P3
= a
a
a
a
a
a
15
14
13
12
11
10
BSP_P0
= 0000 0000
BSP_P1
= a
a
a
a
a
a
a
1
7
6
5
4
3
2
1
BSP_P2
= a
a
a
a
a
a
15
14
13
12
11
10
BSP_P3
= a
a
a
a
a
a
23
22
21
20
19
18
BSP_P0
= a
a
a
a
a
a
a
1
7
6
5
4
3
2
1
BSP_P1
= a
a
a
a
a
a
15
14
13
12
11
10
BSP_P2
= a
a
a
a
a
a
23
22
21
20
19
18
BSP_P3
= a
a
a
a
a
a
31
30
29
28
27
26
SWRU191F – April 2009 – Revised April 2014
www.ti.com
32
x
p
31
31
d
31
Input
1
x
+ 1, where all a
1
n
, and P[0]
n
PRF_CRC_INIT
PRF_CRC_INIT[0]
PRF_CRC_INIT[1]
PRF_CRC_INIT[2]
PRF_CRC_INIT[3]
PRF_CRC_INIT[0]
PRF_CRC_INIT[1]
PRF_CRC_INIT[2]
PRF_CRC_INIT[3]
a
a
9
8
PRF_CRC_INIT[0]
PRF_CRC_INIT[1]
PRF_CRC_INIT[2]
a
a
9
8
PRF_CRC_INIT[3]
a
a
17
16
PRF_CRC_INIT[0]
PRF_CRC_INIT[1]
a
a
9
8
PRF_CRC_INIT[2]
a
a
17
16
a
a
PRF_CRC_INIT[3]
25
24
Submit Documentation Feedback
Output
B0468-01
are 0
= 0
= 0
= 0
= X
= 0
= 0
= X
= X
= 0
= X
= X
= X
= X
= X
= X
= X
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