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System
clock
20.1 Operation
2
The I
C module supports any slave or master I
2
2
I
C bus. Each I
C device is recognized by a unique address and can operate as either a transmitter or a
receiver. A device connected to the I
performing data transfers. A master initiates a data transfer and generates the clock signal, SCL. Any
device addressed by a master is considered a slave.
2
I
C data is communicated using the serial data (SDA) pin and the serial clock (SCL) pin. Both SDA and
SCL are bidirectional and must be connected to a positive supply voltage using a pullup resistor.
SWRU191F – April 2009 – Revised April 2014
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Address register (I2CADDR)
Address comparator
Data shift register (I2CDATA)
Arbitration and synchronization logic
Serial clock generator
Control register (I2CCFG)
Status register (I2CSTAT)
Figure 20-1. Block Diagram of the I
2
C bus can be considered as the master or the slave when
Copyright © 2009–2014, Texas Instruments Incorporated
ACK
Interrupt
Control
logic
2
C Module
2
C-compatible device.
Figure 20-2
Operation
SDA
SCL
P2
interrupt
shows an example of an
169
2
I
C
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