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Radio Test Output Signals
7.9
Radio Test Output Signals
By using the OBSSELx registers (OBSSEL0–OBSSEL5) the user can output different signals from the RF
Core to GPIO pins. These signals can be useful for debugging of low-level protocols or control of external
PA, LNA, or switches. The control registers OBSSEL0–OBSSEL5 can be used to override the standard
GPIO behavior and output RF Core signals (rfc_obs_sig0, rfc_obs_sig1, and rfc_obs_sig2) on
the pins P1[0:5]. For a list of available signals, see the respective RFC_OBS_CTRLx registers in
Section 23.15.3
for CC253x or
7.10 Power-Down Signal MUX (PMUX)
The PMUX register can be used to output the 32-kHz clock and/or the digital voltage regulator status.
The selected 32-kHz clock source can be output on one of the P0 pins. The enable bit CKOEN enables the
output on P0, and the pin of P0 is selected using the CKOPIN (see the PMUX register description for
details). When CKOEN is set, all other configurations for the selected pin are overridden. The clock is
output in all power modes; however, in PM3 the clock stops (see PM3 in
Furthermore, the digital voltage regulator status can be output on one of the P1 pins. When the DREGSTA
bit is set, the status of the digital voltage regulator is output. DREGSTAPIN selects the P1 pin (see the
PMUX register description for details). When DREGSTA is set, all other configurations for the selected pin
are overridden. The selected pin outputs 1 when the 1.8-V on-chip digital voltage regulator is powered up
(chip has regulated power). The selected pin outputs 0 when the 1.8-V on-chip digital voltage regulator is
powered down, that is, in PM2 and PM3.
7.11 I/O Registers
The registers for the I/O ports are described in this section. The registers are:
•
P0: Port 0
•
P1: Port 1
•
P2: Port 2
•
PERCFG: Peripheral-control register
•
APCFG: Analog peripheral I/O configuration
•
P0SEL: Port 0 function-select register
•
P1SEL: Port 1 function-select register
•
P2SEL: Port 2 function-select register
•
P0DIR: Port 0 direction register
•
P1DIR: Port 1 direction register
•
P2DIR: Port 2 direction register
•
P0INP: Port 0 input-mode register
•
P1INP: Port 1 input-mode register
•
P2INP: Port 2 input-mode register
•
P0IFG: Port 0 interrupt-status flag register
•
P1IFG: Port 1 interrupt-status flag register
•
P2IFG: Port 2 interrupt-status flag register
•
PICTL: Interrupt edge register
•
P0IEN: Port 0 interrupt-mask register
•
P1IEN: Port 1 interrupt-mask register
•
P2IEN: Port 2 interrupt-mask register
•
PMUX: Power-down signal-mux register
•
OBSSEL0: Observation output control register 0
•
OBSSEL1: Observation output control register 1
•
OBSSEL2: Observation output control register 2
84
I/O Ports
Section 24.1
for CC2540 or
Copyright © 2009–2014, Texas Instruments Incorporated
Chapter 25
for CC2541.
Chapter
4).
SWRU191F – April 2009 – Revised April 2014
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