Power-Management Registers - Texas Instruments CC253x User Manual

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The instruction that sets the PCON.IDLE bit must be aligned in a certain way for correct operation. The
first byte of the assembly instruction immediately following this instruction must not be placed on a 4-byte
boundary. Furthermore, cache must not be disabled (see CM in the FCTL register description in
Chapter 6). Failure to comply with this requirement may cause higher current consumption. Provided this
requirement is fulfilled, the first assembly instruction after the instruction that sets the PCON.IDLE bit is
performed before the ISR of the interrupt that caused the system to wake up, but after the system woke
up. If this instruction is a global interrupt disable, it is possible to have it followed by code for execution
after wakeup, but before the ISR is serviced.
An example of how this can be done in the IAR compiler is shown as follows. The command for setting
PCON to 1 is placed in a function written in assembly code. In a C file calling this function, a declaration
such as extern void
EnterSleepModeDisableInterruptsOnWakeup(void); is used. The
RSEG NEAR_CODE:CODE:NOROOT(2) statement ensures that the MOV PCON,#1 instruction is placed on
a 2-byte boundary. It is a 3-byte instruction, so the following instruction is not placed on a 4-byte
boundary, as required. In the following example, this instruction is CLR EA, which disables all interrupts.
That means that the ISR of the interrupt that woke up the system is not executed until after the IEN0.EA
bit has been set again later in the code. If this functionality is not wanted, the CLR EA instruction can be
replaced by a NOP.
PUBLIC EnterSleepModeDisableInterruptsOnWakeup FUNCTION
EnterSleepModeDisableInterruptsOnWakeup,0201H RSEG NEAR_CODE:CODE:NOROOT(2)
EnterSleepModeDisableInterruptsOnWakeup: MOV PCON,#1 CLR EA RET
4.3

Power-Management Registers

This section describes the power-management registers. All register bits retain their previous values when
entering PM2 or PM3.
SRCRC (0x6262) – Sleep Reset CRC (CC2533 and CC2541 only)
Bit Name
7 XOSC_AMP_DET_EN
6 –
5 FORCE_RESET
4 –
3:2 CRC_RESULT
1 –
0 CRC_RESET_EN
PCON (0x87) – Power Mode Control
Bit Name
7:1 –
0 IDLE
SWRU191F – April 2009 – Revised April 2014
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Reset R/W
0 R/W 0: Disable
1: Enable the amplitude detector for the 32-MHz XOSC, CC2533 only
0 R0 Reserved. Always read 0.
0 R/W 0: No action
1: Force watchdog reset.
0 R Reserved
00 R/W0 00: CRC of retained registers passed
01: Low CRC value failed
10: High CRC value failed
11: Both CRC values failed
0 R Reserved
0 R/W 0: Disable reset of chip due to CRC.
1: Enable reset of chip if CRC_RESULT != 00 after wakeup from PM2 or PM3.
Reset R/W
0000 000 R/W Reserved, always write as 0000 000.
0 R0/W Power mode control. Writing 1 to this bit forces the device to enter the power mode
set by SLEEPCMD.MODE (note that MODE = 0x00 AND IDLE = 1 stops the CPU core
H0
activity). This bit is always read as 0.
All enabled interrupts clear this bit when active, and the device re-enters active
mode.
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Power-Management Registers
Description
Description
Power Management and Clocks
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