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17.1.4 UART Character Format
If the BIT9 and PARITY bits in register UxUCR are set high, parity generation and detection is enabled.
The parity is computed and transmitted as the ninth bit, and during reception, the parity is computed and
compared to the received ninth bit. If there is a parity error, the UxCSR.ERR bit is set high. This bit is
cleared when UxCSR is read.
The number of stop bits to be transmitted is set to one or two bits, as determined by the register bit
UxUCR.SPB. The receiver always checks for one stop bit. If the first stop bit received during reception is
not at the expected stop bit level, a framing error is signaled by setting register bit UxCSR.FE high.
UxCSR.FE is cleared when UxCSR is read. The receiver checks both stop bits when UxUCR.SPB is set.
Note that the RX interrupt is set when the first stop bit is checked OK. If second stop bit is not OK, there is
a delay in setting the framing error bit, UxCSR.FE. This delay is baud-rate dependent (bit duration).
17.2 SPI Mode
This section describes the SPI mode of operation for synchronous communication. In SPI mode, the
USART communicates with an external system through a three-wire or four-wire interface. The interface
consists of the pins MOSI, MISO, SCK, and SS_N. See
pins are assigned to the I/O pins.
The SPI mode includes the following features:
•
Three-wire (master) and four-wire SPI interface
•
Master and slave modes
•
Configurable SCK polarity and phase
•
Configurable LSB- or MSB-first transfer
The SPI mode is selected when UxCSR.MODE is set to 0.
In SPI mode, the USART can be configured to operate either as a SPI master or as a SPI slave by writing
the UxCSR.SLAVE bit.
17.2.1 SPI Master Operation
A SPI byte transfer in master mode is initiated when the UxDBUF register is written. The USART generates
the SCK serial clock using the baud-rate generator (see
the transmit register onto the MOSI output. At the same time, the receive register shifts in the received
byte from the MISO input pin.
The UxCSR.ACTIVE bit goes high when the transfer starts and low when the transfer ends. When the
transfer ends, the UxCSR.TX_BYTE bit is set to 1.
The polarity and clock phase of the serial clock SCK is selected by UxGCR.CPOL and UxGCR.CPHA. The
order of the byte transfer is selected by the UxGCR.ORDER bit.
At the end of the transfer, the received data byte is available for reading from the UxDBUF. A receive
interrupt is generated when this new data is ready in the UxDBUF USART receive- and transmit-data
register.
A transmit interrupt is generated when the unit is ready to accept another data byte for transmission.
Because UxDBUF is double-buffered, this happens just after the transmission has been initiated. Note that
data should not be written to UxDBUF until UxCSR.TX_BYTE is 1. For DMA transfers, this is handled
automatically. For back-to-back transmits using DMA, the UxGCR.CPHA bit must be set to zero; if not,
transmitted bytes can become corrupted. For systems requiring setting of UxGCR.CPHA, polling
UxCSR.TX_BYTE is needed.
Also, note the difference between transmit interrupt and receive interrupt, as the former arrives
approximately eight bit-periods prior to the latter.
SPI master-mode operation as described previously is a three-wire interface. No select input is used to
enable the master. If the external slave requires a slave-select signal, this can be implemented through
software using a general-purpose I/O pin.
SWRU191F – April 2009 – Revised April 2014
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Copyright © 2009–2014, Texas Instruments Incorporated
Section 7.6
for a description of how the USART
Section
17.4) and shifts the provided byte from
UART Mode
157
USART
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